[coreboot-gerrit] Patch set updated for coreboot: google: nyan_big: Match CBFS_SIZE with cbfs size in fmap for ChromeOS

[Paul Kocialkowski (contact@paulk.fr)]

Paul Kocialkowski (contact at paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14474

-gerrit

commit 2363b1cdebf4065142a1d96394b2422d3f958291
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Fri Apr 22 15:13:18 2016 +0200

    google: nyan_big: Match CBFS_SIZE with cbfs size in fmap for ChromeOS
    
    When building for ChromeOS, it is expected that Coreboot will only use
    the first MiB of the SPI flash, according to the nyan fmap description.
    Otherwise, it makes sense to use the full ROM size.
    
    Change-Id: I88f444c99abec340c778fd0a56972e16d2d63c4f
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 src/mainboard/google/nyan_big/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index fdd40f6..c0cbc62 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -95,6 +95,11 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x20
 
+config CBFS_SIZE
+	hex
+	default 0x100000 if CHROMEOS
+	default ROM_SIZE
+
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string
 	default "big"