[coreboot-gerrit] Patch merged into coreboot/master: nb/amd/mct_ddr3: Disable MCE framework during DRAM training
gerrit at coreboot.org
gerrit at coreboot.org
Thu Mar 31 20:00:37 CEST 2016
the following patch was just integrated into master:
commit c094d9961144871c472698c41ce634e58abb6a32
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Tue Mar 29 20:37:36 2016 -0500
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
On Family 15h processors, with certain RDIMMs, MCEs are generated
as a normal part of DCT startup / DRAM training. Disable sync
flood on parity or UC data error until ECC has been enabled.
Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14186
Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth at google.com>
See https://review.coreboot.org/14186 for details.
-gerrit
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