[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: utilize postcar phase/stage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit eebe0e0db14476dde980896b8eb8a97129436af3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 18 11:19:38 2016 -0500

    soc/intel/apollolake: utilize postcar phase/stage
    
    The current Apollolake flow has its code executing out of
    cache-as-ram for the pre-DRAM stages. This is different from
    past platforms where they were just executing-in-place against
    the memory-mapped SPI flash boot media. The implication is
    that when cache-as-ram needs to be torn down one needs to be
    executing out of DRAM since the act of cache-as-ram going
    away means the code disappears out from under the processor.
    Therefore load and use the postcar infrastructure to bootstrap
    this process for tearing down cache-as-ram and subsequently
    loading ramstage.
    
    Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/14141
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/14141 for details.

-gerrit