[coreboot-gerrit] New patch to review for coreboot: nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14148

-gerrit

commit d81baf1817618e572eb7efd39383de1f338e27f3
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Mon Mar 21 02:14:50 2016 -0500

    nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
    
    Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index da71816..9a0d372 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1555,7 +1555,6 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat)
 {
 	u8 Channel;
-	u8 Addl_Index = 0;
 	u8 Receiver;
 	u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0;
 	u32 Errors;
@@ -1629,10 +1628,9 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 		 * This is essentially looping over each DIMM.
 		 */
 		for (; Receiver < 8; Receiver += 2) {
-			Addl_Index = (Receiver >> 1) * 3 + 0x10;
 			dimm = (Receiver >> 1);
 
-			print_debug_dqs("\t\tTrainMaxRdLatency52: index ", Addl_Index, 2);
+			print_debug_dqs("\t\tTrainMaxRdLatency52: Receiver ", Receiver, 2);
 
 			if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) {
 				continue;