[coreboot-gerrit] New patch to review for coreboot: Documentation: x86 shadow ROM disable

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14112

-gerrit

commit c55a0cb91caf68b3f4d5cf1a53ac346017ef037c
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sun Jan 31 11:28:06 2016 -0800

    Documentation: x86 shadow ROM disable
    
    Add documentation on disabling the SPI flash which is mapped (shadowed)
    into the x86 address space at 0x000e0000 - 0x000fffff.
    
    TEST=None
    
    Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
    Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
 Documentation/Intel/SoC/soc.html     | 14 +++++++++++++-
 Documentation/Intel/development.html | 12 +++++++++++-
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 2380cdf..8f1d75c 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -24,6 +24,7 @@
       <li>Enable <a href="#SerialOutput">Serial Output"</a></li>
       <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
       <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
+      <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li>
     </ol>
   </li>
   <li><a href="#Ramstage">Ramstage</a>
@@ -389,6 +390,17 @@ Use the following steps to debug the call to TempRamInit:
 </ol>
 
 
+<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2>
+<p>
+  A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.
+  This shadow needs to be disabled to allow RAM to properly respond to
+  this address range.
+</p>
+<ol>
+  <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li>
+</ol>
+
+
 <hr>
 <h1><a name="Ramstage">Ramstage</a></h1>
 
@@ -717,6 +729,6 @@ Use the following steps to debug the call to TempRamInit:
 </table>
 
 <hr>
-<p>Modified: 28 February 2016</p>
+<p>Modified: 4 March 2016</p>
   </body>
 </html>
\ No newline at end of file
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 7b82321..a36acaa 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -94,6 +94,9 @@
       </li>
     </ol>
   </li>
+  <li>Disable the
+    <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
+  </li>
   <li>
     Implement the .init routine for the
     <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
@@ -198,6 +201,13 @@
       for the PCI devices on the bus.
     </td>
   </tr>
+  <tr>
+    <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
+    <td>
+      Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
+    </td>
+    <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
+  </tr>
 
 
   <tr bgcolor="#c0ffc0">
@@ -346,6 +356,6 @@
 
 
 <hr>
-<p>Modified: 24 February 2016</p>
+<p>Modified: 4 March 2016</p>
   </body>
 </html>
\ No newline at end of file