[coreboot-gerrit] Patch set updated for coreboot: rockchip: rk3399: add grf define
Lin Huang (hl@rock-chips.com)
gerrit at coreboot.org
Tue Mar 15 10:17:21 CET 2016
Lin Huang (hl at rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13917
-gerrit
commit 9df567d9b96d3e1547290fe3c8f8fd0b19111c29
Author: Lin Huang <hl at rock-chips.com>
Date: Mon Mar 7 18:43:12 2016 +0800
rockchip: rk3399: add grf define
add grf define, we can do iomux and secure setting
Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa
Signed-off-by: huang lin <hl at rock-chips.com>
---
src/mainboard/google/gru/bootblock.c | 14 ++
src/soc/rockchip/rk3399/bootblock.c | 13 ++
src/soc/rockchip/rk3399/include/soc/grf.h | 295 ++++++++++++++++++++++++++++++
3 files changed, 322 insertions(+)
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index bdc75dd..ce6f7c0 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -14,12 +14,26 @@
*
*/
+#include <arch/io.h>
+#include <assert.h>
#include <bootblock_common.h>
+#include <soc/grf.h>
+#include <soc/spi.h>
+#include <console/console.h>
void bootblock_mainboard_early_init(void)
{
+ if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+ assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
+ write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
+
+ /* grf soc_con7[11:10] use for uart2 select*/
+ write32(&rk3399_grf->soc_con7, UART2C_SEL);
+ }
}
void bootblock_mainboard_init(void)
{
+ write32(&rk3399_grf->iomux_spi2, IOMUX_SPI2);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
}
diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c
index dc604a1..03075ab 100644
--- a/src/soc/rockchip/rk3399/bootblock.c
+++ b/src/soc/rockchip/rk3399/bootblock.c
@@ -18,10 +18,23 @@
#include <arch/mmu.h>
#include <bootblock_common.h>
#include <console/console.h>
+#include <soc/grf.h>
#include <soc/mmu_operations.h>
#include <symbols.h>
void bootblock_soc_init(void)
{
+ /* all ddr range non-secure */
+ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
+
+ /* tzma_rosize = 0, all sram non-serure */
+ write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
+
+ /* emmc master secure*/
+ write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
+
+ /* glb_slv_secure_bypass */
+ write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
+
rockchip_mmu_init();
}
diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h
new file mode 100644
index 0000000..96c2fed
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/grf.h
@@ -0,0 +1,295 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
+#define __SOC_ROCKCHIP_RK3399_GRF_H__
+
+#include <soc/addressmap.h>
+#include <soc/soc.h>
+#include <types.h>
+
+struct rk3399_grf_regs {
+ u32 reserved[0x800];
+ u32 usb3_perf_con0;
+ u32 usb3_perf_con1;
+ u32 usb3_perf_con2;
+ u32 usb3_perf_rd_max_latency_num;
+ u32 usb3_perf_rd_latency_samp_num;
+ u32 usb3_perf_rd_latency_acc_num;
+ u32 usb3_perf_rd_axi_total_byte;
+ u32 usb3_perf_wr_axi_total_byte;
+ u32 usb3_perf_working_cnt;
+ u32 reserved1[0x103];
+ u32 usb3otg0_con0;
+ u32 usb3otg0_con1;
+ u32 reserved2[2];
+ u32 usb3otg1_con0;
+ u32 usb3otg1_con1;
+ u32 reserved3[2];
+ u32 usb3otg0_status_lat0;
+ u32 usb3otg0_status_lat1;
+ u32 usb3otg0_status_cb;
+ u32 reserved4;
+ u32 usb3otg1_status_lat0;
+ u32 usb3otg1_status_lat1;
+ u32 usb3ogt1_status_cb;
+ u32 reserved5[0x6e5];
+ u32 pcie_perf_con0;
+ u32 pcie_perf_con1;
+ u32 pcie_perf_con2;
+ u32 pcie_perf_rd_max_latency_num;
+ u32 pcie_perf_rd_latency_samp_num;
+ u32 pcie_perf_rd_laterncy_acc_num;
+ u32 pcie_perf_rd_axi_total_byte;
+ u32 pcie_perf_wr_axi_total_byte;
+ u32 pcie_perf_working_cnt;
+ u32 reserved6[0x37];
+ u32 usb20_host0_con0;
+ u32 usb20_host0_con1;
+ u32 reserved7[2];
+ u32 usb20_host1_con0;
+ u32 usb20_host1_con1;
+ u32 reserved8[2];
+ u32 hsic_con0;
+ u32 hsic_con1;
+ u32 reserved9[6];
+ u32 grf_usbhost0_status;
+ u32 grf_usbhost1_Status;
+ u32 grf_hsic_status;
+ u32 reserved10[0xc9];
+ u32 hsicphy_con0;
+ u32 reserved11[3];
+ u32 usbphy0_ctrl[26];
+ u32 reserved12[6];
+ u32 usbphy1[26];
+ u32 reserved13[0x72f];
+ u32 soc_con9;
+ u32 reserved14[0x0a];
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 soc_con22;
+ u32 soc_con23;
+ u32 soc_con24;
+ u32 soc_con25;
+ u32 soc_con26;
+ u32 reserved15[0xf65];
+ u32 cpu_con[4];
+ u32 reserved16[0x1c];
+ u32 cpu_status[6];
+ u32 reserved17[0x1a];
+ u32 a53_perf_con[4];
+ u32 a53_perf_rd_mon_st;
+ u32 a53_perf_rd_mon_end;
+ u32 a53_perf_wr_mon_st;
+ u32 a53_perf_wr_mon_end;
+ u32 a53_perf_rd_max_latency_num;
+ u32 a53_perf_rd_latency_samp_num;
+ u32 a53_perf_rd_laterncy_acc_num;
+ u32 a53_perf_rd_axi_total_byte;
+ u32 a53_perf_wr_axi_total_byte;
+ u32 a53_perf_working_cnt;
+ u32 a53_perf_int_status;
+ u32 reserved18[0x31];
+ u32 a72_perf_con[4];
+ u32 a72_perf_rd_mon_st;
+ u32 a72_perf_rd_mon_end;
+ u32 a72_perf_wr_mon_st;
+ u32 a72_perf_wr_mon_end;
+ u32 a72_perf_rd_max_latency_num;
+ u32 a72_perf_rd_latency_samp_num;
+ u32 a72_perf_rd_laterncy_acc_num;
+ u32 a72_perf_rd_axi_total_byte;
+ u32 a72_perf_wr_axi_total_byte;
+ u32 a72_perf_working_cnt;
+ u32 a72_perf_int_status;
+ u32 reserved19[0x7f6];
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 reserved20[0x779];
+ u32 gpio2a_iomux;
+ union {
+ u32 iomux_spi2;
+ u32 gpio2b_iomux;
+ };
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+ u32 gpio4a_iomux;
+ union {
+ u32 iomux_uart2a;
+ u32 gpio4b_iomux;
+ };
+ union {
+ u32 iomux_uart2b;
+ u32 iomux_uart2c;
+ u32 gpio4c_iomux;
+ };
+ u32 gpio4d_iomux;
+ u32 reserved21[4];
+ u32 gpio2_p[3][4];
+ u32 reserved22[4];
+ u32 gpio2_sr[3][4];
+ u32 reserved23[4];
+ u32 gpio2_smt[3][4];
+ u32 reserved24[0x44];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5_pcie;
+ u32 reserved25;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9_pcie;
+ u32 reserved26[0x1e];
+ u32 soc_status[6];
+ u32 reserved27[0x32];
+ u32 ddrc0_con0;
+ u32 ddrc0_con1;
+ u32 ddrc1_con0;
+ u32 ddrc1_con1;
+};
+check_member(rk3399_grf_regs, ddrc1_con1, 0xe38c);
+
+struct rk3399_pmugrf_regs {
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 reserved0[2];
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+ u32 reserved1[8];
+ u32 gpio0_p[2][4];
+ u32 reserved3[8];
+ u32 gpio0a_e;
+ u32 reserved4;
+ u32 gpio0b_e;
+ u32 reserved5[5];
+ u32 gpio1a_e;
+ u32 reserved6;
+ u32 gpio1b_e;
+ u32 reserved7;
+ u32 gpio1c_e;
+ u32 reserved8;
+ u32 gpio1d_e;
+ u32 reserved9[0x11];
+ u32 gpio0l_sr;
+ u32 reserved10;
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 reserved11[4];
+ u32 gpio0a_smt;
+ u32 gpio0b_smt;
+ u32 reserved12[2];
+ u32 gpio1a_smt;
+ u32 gpio1b_smt;
+ u32 gpio1c_smt;
+ u32 gpio1d_smt;
+ u32 reserved13[8];
+ u32 gpio0l_he;
+ u32 reserved14;
+ u32 gpio1l_he;
+ u32 gpio1h_he;
+ u32 reserved15[4];
+ u32 soc_con0;
+ u32 reserved16[9];
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 reserved17[0x24];
+ u32 pmupvtm_con0;
+ u32 pmupvtm_con1;
+ u32 pmupvtm_status0;
+ u32 pmupvtm_status1;
+ u32 grf_osc_e;
+ u32 reserved18[0x2b];
+ u32 os_reg0;
+ u32 os_reg1;
+ u32 os_reg2;
+ u32 os_reg3;
+};
+check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
+
+struct rk3399_pmusgrf_regs {
+ u32 ddr_rgn_con[35];
+ u32 reserved[0x1fe5];
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 reserved1[3];
+ u32 soc_con19;
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 soc_con22;
+ u32 reserved2[0x29];
+ u32 perilp_con[9];
+ u32 reserved4[7];
+ u32 perilp_status;
+ u32 reserved5[0xfaf];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 reserved6[0x3e];
+ u32 pmu_con[9];
+ u32 reserved7[0x17];
+ u32 fast_boot_addr;
+ u32 reserved8[0x1f];
+ u32 efuse_prg_mask;
+ u32 efuse_read_mask;
+ u32 reserved9[0x0e];
+ u32 pmu_slv_con0;
+ u32 pmu_slv_con1;
+ u32 reserved10[0x771];
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 reserved11[8];
+ u32 soc_con16;
+ u32 soc_con17;
+ u32 soc_con18;
+ u32 reserved12[0xdd];
+ u32 slv_secure_con0;
+ u32 slv_secure_con1;
+ u32 reserved13;
+ u32 slv_secure_con2;
+ u32 slv_secure_con3;
+ u32 slv_secure_con4;
+};
+check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
+
+static struct rk3399_grf_regs * const rk3399_grf = (void *)GRF_BASE;
+static struct rk3399_pmugrf_regs * const rk3399_pmugrf = (void *)PMUGRF_BASE;
+static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE;
+
+#define UART2A_SEL RK_CLRSETBITS(3 << 10, 0 << 10)
+#define UART2B_SEL RK_CLRSETBITS(3 << 10, 1 << 10)
+#define UART2C_SEL RK_CLRSETBITS(3 << 10, 2 << 10)
+
+#define IOMUX_UART2A RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0)
+#define IOMUX_UART2B RK_CLRSETBITS(3 << 2 | 3 << 0, 2 << 2 | 2 << 0)
+#define IOMUX_UART2C RK_CLRSETBITS(3 << 8 | 3 << 6, 1 << 8 | 1 << 6)
+#define IOMUX_SPI2 RK_CLRSETBITS(0xff << 2, 1 << 8 | 1 << 6 | 1 << 4 | 1 << 2)
+
+#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */
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