[coreboot-gerrit] Patch merged into coreboot/master: nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
gerrit at coreboot.org
gerrit at coreboot.org
Fri Mar 11 16:58:11 CET 2016
the following patch was just integrated into master:
commit 50583f0e1f82f6863762c75acf01c26e163bf2da
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Tue Mar 8 18:40:28 2016 -0600
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency
must be calculated prior to DQS position training, however the read
latency calculations use read DQS delay values that have not been
set prior to DQS position training.
Set the read DQS delay values to 1UI (i.e worst case) before calculating
the read latency prior to DQS position training.
Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13995
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth at google.com>
See https://review.coreboot.org/13995 for details.
-gerrit
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