[coreboot-gerrit] Patch set updated for coreboot: northbridge/i945/gma: Re-enable NVRAM tft_brightness
Alexander Couzens (lynxis@fe80.eu)
gerrit at coreboot.org
Thu Mar 10 12:59:02 CET 2016
Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14002
-gerrit
commit d0cdee89d8477a89d769b981e66bef1566947373
Author: Alexander Couzens <lynxis at fe80.eu>
Date: Wed Mar 9 10:42:58 2016 +0100
northbridge/i945/gma: Re-enable NVRAM tft_brightness
Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init)
unintentionally changed the code to ignore the NVRAM setting
`tft_brightness`. Revert that hunk to restore the original behavior.
Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
src/northbridge/intel/i945/gma.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index bd0a178..df13ef4 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -465,14 +465,17 @@ static void gma_func0_disable(struct device *dev)
static void gma_func1_init(struct device *dev)
{
u32 reg32;
+ u8 val;
/* IGD needs to be Bus Master, also enable IO accesss */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */
- pci_write_config8(dev, 0xf4, 0xff);
+ if (get_option(&val, "tft_brightness") == CB_SUCCESS)
+ pci_write_config8(dev, 0xf4, val);
+ else
+ pci_write_config8(dev, 0xf4, 0xff);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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