[coreboot-gerrit] Patch merged into coreboot/master: intel/fsp_baytrail: use 20K PU/PD for GPIO

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2ae9cce87a9aee32b465a50d8ea3bb888c97eb68
Author: Ben Gardner <gardner.ben at gmail.com>
Date:   Fri Mar 4 16:42:08 2016 -0600

    intel/fsp_baytrail: use 20K PU/PD for GPIO
    
    The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs.
    The 10K and 40K values map to 'reserved'.
    
    This brings the code closer to the non-FSP baytrail.
    
    Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03
    Signed-off-by: Ben Gardner <gardner.ben at gmail.com>
    Reviewed-on: https://review.coreboot.org/13907
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13907 for details.

-gerrit