[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798

-gerrit

commit 283b0619e3bc6659ad8042b2cfe99d1f15efa126
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Feb 25 14:16:33 2016 -0800

    drivers/intel/fsp2_0: Add MemoryInit API
    
    This adds implementation of fsp_memory_init() that is used to train
    memory.
    
    Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h | 11 ++--
 src/drivers/intel/fsp2_0/memory_init.c     | 88 ++++++++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 0d45df3..6b11055 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -16,6 +16,8 @@
 #include <stddef.h>
 #include <memrange.h>
 #include <fsp/info_header.h>
+#include <fsp/FspmUpd.h>
+#include <fsp/FspsUpd.h>
 
 enum fsp_status {
 	FSP_SUCCESS = 0x00000000,
@@ -39,19 +41,14 @@ enum fsp_notify_phase {
 };
 
 
-/* Opaque structures. These are platform-specific. */
-struct FSP_M_CONFIG;
-struct FSP_S_CONFIG;
-
 /* Main FSP stages */
 enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
 enum fsp_status fsp_silicon_init(struct range_entry *r);
 enum fsp_status fsp_notify(enum fsp_notify_phase phase);
 
 /* Callbacks for updating stage-specific parameters */
-void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd,
-					struct FSP_M_CONFIG *mcfg);
-void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd);
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
 
 /*
  * # DOCUMENTATION:
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
new file mode 100644
index 0000000..73a36cf
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memrange.h>
+#include <string.h>
+#include <timestamp.h>
+#include <fsp/FspmUpd.h>
+
+struct fsp_memory_init_params {
+	void *nvs_buffer;
+	void *raminit_upd;
+	void **hob_list;
+} __attribute__ ((__packed__));
+
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+				   (struct fsp_memory_init_params *);
+
+static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
+					  struct fsp_header *hdr)
+{
+	enum fsp_status status;
+	fsp_memory_init_fn fsp_raminit;
+	struct fsp_memory_init_params raminit_params;
+	struct FSPM_UPD fspm_upd, *upd;
+
+	post_code(0x34);
+
+	upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+
+	/* If blob has bigger UPD we are probably out of sync*/
+	if (hdr->cfg_region_size > sizeof(fspm_upd)) {
+		printk(BIOS_ERR, "UPD size bigger than expected header size\n");
+		return FSP_OUT_OF_RESOURCES;
+	}
+
+	/* Copy the default values from the UPD area */
+	memcpy(&fspm_upd, upd, sizeof(fspm_upd));
+
+	/* Get any board specific changes */
+	raminit_params.nvs_buffer = NULL;
+	raminit_params.raminit_upd = &fspm_upd;
+	raminit_params.hob_list = hob_list_ptr;
+
+	/* Give SoC and mainboard a chance to update the UPD */
+	platform_fsp_memory_init_params_cb(&fspm_upd);
+
+	/* Call FspMemoryInit */
+	fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+	printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
+	printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer);
+	printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd);
+	printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list);
+
+	timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+	status = fsp_raminit(&raminit_params);
+	post_code(0x37);
+	timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+	printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+
+	return status;
+}
+
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range)
+{
+	struct fsp_header hdr;
+
+	/* TODO: do not hardcode CBFS file names */
+	if (fsp_load_binary(&hdr, "blobs/fspm.bin", range) != CB_SUCCESS)
+		return FSP_NOT_FOUND;
+
+	return do_fsp_memory_init(hob_list, &hdr);
+}