[coreboot-gerrit] Patch set updated for coreboot: [WIP]intel/apollolake: add sd card irq ssdt code
Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)
gerrit at coreboot.org
Thu Jun 30 08:51:50 CEST 2016
Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15515
-gerrit
commit c654d6427f331b80e89019e179d92d83e9d98e0d
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date: Wed Jun 29 23:28:25 2016 -0700
[WIP]intel/apollolake: add sd card irq ssdt code
BUG=chrome-os-partner:54371
TEST=verfiy sd card irq entry in kernel.
Change-Id: I10e61cfbb779c419d6ae92e2b98c8619bd5cf7fb
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/chip.h | 7 ++
src/soc/intel/apollolake/include/soc/pci_ids.h | 1 +
src/soc/intel/apollolake/sd.c | 95 ++++++++++++++++++++++++++
4 files changed, 104 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 7326f14..38adf3d 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -59,6 +59,7 @@ ramstage-y += pmc.c
ramstage-y += reset.c
ramstage-y += smi.c
ramstage-y += spi.c
+ramstage-y += sd.c
postcar-y += exit_car.S
postcar-y += memmap.c
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index ef82c53..02e3894 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -18,6 +18,8 @@
#ifndef _SOC_APOLLOLAKE_CHIP_H_
#define _SOC_APOLLOLAKE_CHIP_H_
+#include <arch/acpi_device.h>
+
#define CLKREQ_DISABLED 0xf
/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
@@ -79,6 +81,11 @@ struct soc_intel_apollolake_config {
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
+
+ /* Use default SD card detect GPIO configuration */
+ unsigned sdcard_cd_gpio_default;
+ /* Use custom SD card detect GPIO configuration */
+ struct acpi_gpio sdcard_cd_gpio;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
index 0790c6e..ca8ae4e 100644
--- a/src/soc/intel/apollolake/include/soc/pci_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -40,6 +40,7 @@
#define PCI_DEVICE_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */
#define PCI_DEVICE_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */
#define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SD 0x5aca /* 00:1b.0 */
#define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */
#endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */
diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c
new file mode 100644
index 0000000..e95fc3f
--- /dev/null
+++ b/src/soc/intel/apollolake/sd.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <soc/pci_ids.h>
+#include "chip.h"
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static void sd_fill_ssdt(struct device *dev)
+{
+ struct soc_intel_apollolake_config *config;
+ const char *path;
+ struct acpi_gpio default_gpio = {
+ .type = ACPI_GPIO_TYPE_INTERRUPT,
+ .pull = ACPI_GPIO_PULL_NONE,
+ .irq.mode = IRQ_EDGE_TRIGGERED,
+ .irq.polarity = IRQ_ACTIVE_BOTH,
+ .irq.shared = IRQ_SHARED,
+ .irq.wake = IRQ_WAKE,
+ .interrupt_debounce_timeout = 10000, /* 100ms */
+ .pin_count = 1,
+ };
+
+ if (!dev->enabled)
+ return;
+
+ config = dev->chip_info;
+ if (!config) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+
+ /* Nothing to write if GPIO is not set in devicetree */
+ if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0])
+ return;
+
+ /* Use device path as the Scope for the SSDT */
+ path = acpi_device_path(dev);
+ if (!path)
+ return;
+
+ acpigen_write_scope(path);
+ acpigen_write_name("_CRS");
+
+ /* Write GpioInt() as default (if set) or custom from devicetree */
+ acpigen_write_resourcetemplate_header();
+ if (config->sdcard_cd_gpio_default) {
+ default_gpio.pins[0] = config->sdcard_cd_gpio_default;
+ acpi_device_write_gpio(&default_gpio);
+ } else
+ acpi_device_write_gpio(&config->sdcard_cd_gpio);
+
+ acpigen_write_resourcetemplate_footer();
+
+ /* Bind the cd-gpio name to the GpioInt() resource */
+ acpi_dp_write_header();
+ acpi_dp_write_gpio("cd-gpio", path, 0, 0, 1);
+ acpi_dp_write_footer();
+
+ acpigen_pop_len();
+}
+#endif
+
+static struct device_operations dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt_generator = &sd_fill_ssdt,
+#endif
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+ .ops = &dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_APOLLOLAKE_SD,
+};
More information about the coreboot-gerrit
mailing list