[coreboot-gerrit] Patch set updated for coreboot: intel post-car: Separate romstage ramstack (WIP)
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Jun 29 10:32:25 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15468
-gerrit
commit 6ad6da894b275c2fdf584978de09cb58afbd05d9
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jun 27 13:24:11 2016 +0300
intel post-car: Separate romstage ramstack (WIP)
TODO: Need to fix MTRRs before placing stack high.
TODO: Check stack top reference in FSP1_0
TODO: Case LATE_CBMEM_INIT
Change-Id: I221e207bcd0031048876f29100a1770a444d435b
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/romstage.c | 20 +++++++++++++++++++-
src/drivers/intel/fsp1_0/fsp_util.c | 3 ++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c6df446..215a6a2 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -1,7 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <cpu/intel/romstage.h>
+#include <program_loading.h>
void * asmlinkage romstage_main(unsigned long bist)
{
mainboard_romstage_entry(bist);
- return (void*)CONFIG_RAMTOP;
+
+ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
+ return (void*)CONFIG_RAMTOP;
+
+ return (void*)romstage_ram_stack_top();
}
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index a3fef2d..1f12053 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -22,6 +22,7 @@
#include <lib.h> // hexdump
#include <ip_checksum.h>
#include <timestamp.h>
+#include <program_loading.h>
#ifndef __PRE_RAM__
/* Globals pointers for FSP structures */
@@ -76,7 +77,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
#endif
memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
- FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
+ FspRtBuffer.Common.StackTop = (u32 *)romstage_ram_stack_top();
FspInitParams.NvsBufferPtr = NULL;
#if IS_ENABLED(CONFIG_FSP_USES_UPD)
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