[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add NHLT table region to ACPI global nvs
Saurabh Satija (saurabh.satija@intel.com)
gerrit at coreboot.org
Tue Jun 28 21:49:27 CEST 2016
Saurabh Satija (saurabh.satija at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025
-gerrit
commit 24c7ff91c5b86e73107019aa3925a55d648674cb
Author: Saurabh Satija <saurabh.satija at intel.com>
Date: Thu Mar 31 15:41:30 2016 -0700
soc/intel/apollolake: Add NHLT table region to ACPI global nvs
Add address and length of NHLT table in ACPI.
Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a
Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
---
src/soc/intel/apollolake/acpi/globalnvs.asl | 2 ++
src/soc/intel/apollolake/include/soc/nvs.h | 14 ++++++++------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 3597788..3f9683f 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
+ NHLA, 64, // 0x09 - NHLT Address
+ NHLL, 32, // 0x11 - NHLT Length
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index fda3556..1ff5f23 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,13 +28,15 @@
struct global_nvs_t {
/* Miscellaneous */
- uint8_t pcnt; /* 0x00 - Processor Count */
- uint8_t ppcm; /* 0x01 - Max PPC State */
- uint8_t lids; /* 0x02 - LID State */
- uint8_t pwrs; /* 0x03 - AC Power State */
- uint8_t dpte; /* 0x04 - Enable DPTF */
+ uint8_t pcnt; /* 0x00 - Processor Count */
+ uint8_t ppcm; /* 0x01 - Max PPC State */
+ uint8_t lids; /* 0x02 - LID State */
+ uint8_t pwrs; /* 0x03 - AC Power State */
+ uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
- uint8_t unused[247];
+ uint64_t nhla; /* 0x09 - NHLT Address */
+ uint32_t nhll; /* 0x11 - NHLT Length */
+ uint8_t unused[235];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
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