[coreboot-gerrit] New patch to review for coreboot: apollolake: Add function to translate device into ACPI name
Duncan Laurie (dlaurie@chromium.org)
gerrit at coreboot.org
Tue Jun 28 20:35:52 CEST 2016
Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15479
-gerrit
commit e2f6dda724451687c0fe40477179a132f92073c4
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Mon Jun 27 10:51:17 2016 -0700
apollolake: Add function to translate device into ACPI name
Add support for the soc_acpi_name() handler in the device operations
structure to translate a device path into ACPI name.
In order to make this more complete add some missing devices in
include/soc/pci_devs.h.
Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/soc/intel/apollolake/chip.c | 58 +++++++++++++++++++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 18 ++++++++
2 files changed, 76 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 821570b..79cde2e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -39,6 +39,63 @@
static void *vbt;
static struct region_device vbt_rdev;
+static const char *soc_acpi_name(struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ /* DSDT: acpi/northbridge.asl */
+ case NB_DEVFN:
+ return "MCHC";
+ case PCI_DEVFN(0x1f, 0):
+ /* DSDT: acpi/lpc.asl */
+ return "LPCB";
+ /* DSDT: acpi/xhci.asl */
+ case PCI_DEVFN(0x15, 0):
+ return "XHCI";
+ /* DSDT: acpi/lpss.asl */
+ case PCI_DEVFN(LPSS_DEV_SLOT_UART, 0):
+ return "URT1";
+ case PCI_DEVFN(LPSS_DEV_SLOT_UART, 1):
+ return "URT2";
+ case PCI_DEVFN(LPSS_DEV_SLOT_UART, 2):
+ return "URT3";
+ case PCI_DEVFN(LPSS_DEV_SLOT_UART, 3):
+ return "URT4";
+ case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 0):
+ return "SPI1";
+ case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 1):
+ return "SPI2";
+ case PCI_DEVFN(LPSS_DEV_SLOT_SPI, 2):
+ return "SPI3";
+ case PCI_DEVFN(LPSS_DEV_SLOT_PWM, 0):
+ return "PWM";
+ /* SSDT: i2c.c */
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 0):
+ return "I2C0";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 1):
+ return "I2C1";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 2):
+ return "I2C2";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_0123, 3):
+ return "I2C3";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 0):
+ return "I2C4";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 1):
+ return "I2C5";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 2):
+ return "I2C6";
+ case PCI_DEVFN(LPSS_DEV_SLOT_I2C_4567, 3):
+ return "I2C7";
+ }
+
+ return NULL;
+}
+
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
@@ -51,6 +108,7 @@ static struct device_operations pci_domain_ops = {
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
+ .acpi_name = &soc_acpi_name,
};
static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index fc046d1..ec2674d 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -39,12 +39,30 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+/* LPSS I2C */
+#define LPSS_DEV_SLOT_I2C_0123 0x16 /* I2C bus 0-3 */
+#define LPSS_DEV_SLOT_I2C_4567 0x17 /* I2C bus 4-7 */
+
+/* LPSS SPI */
+#define LPSS_DEV_SLOT_SPI 0x19
+
+/* LPSS PWM */
+#define LPSS_DEV_SLOT_PWM 0x1a
+
#define NB_BUS 0
#define NB_DEVFN PCI_DEVFN(0, 0)
#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0)
+
+#define P2SB_DEVFN PCI_DEVFN(0xd, 0)
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+
+#define PMC_DEVFN PCI_DEVFN(0xd, 1)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#define SPI_DEVFN PCI_DEVFN(0xd, 2)
#define SPI_DEV PCI_DEV(0, 0xd, 2)
+
+#define LPC_DEVFN PCI_DEVFN(0x1f, 0)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define ISH_DEVFN PCI_DEVFN(0x11, 0)
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