[coreboot-gerrit] Patch set updated for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Tue Jun 28 00:27:09 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453
-gerrit
commit b7955747ce115d8d22867f80562c36902d9fe2d4
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Mon Jun 27 15:21:26 2016 -0700
WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
As whole 1024 KiB is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used
to setup it. This is part of preparation for CQOS enabling.
BUG=chrome-os-partner:51959
Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Kconfig | 2 +-
src/soc/intel/apollolake/bootblock/cache_as_ram.S | 26 +++++++++++++++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 98ce7d8..f51dbfb 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -77,7 +77,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
- default 0x100000
+ default 0xc0000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
index 8647206..a362969 100644
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
@@ -70,6 +70,31 @@ clear_var_mtrr:
post_code(0x24)
+#if (CONFIG_DCACHE_RAM_SIZE == 0xc0000) /* 768 KiB */
+ /* 512 KiB */
+ mov $MTRR_PHYS_BASE(0), %ecx
+ mov $CONFIG_DCACHE_RAM_BASE, %eax
+ or $MTRR_TYPE_WRBACK, %eax
+ xor %edx,%edx
+ wrmsr
+
+ mov $MTRR_PHYS_MASK(0), %ecx
+ mov $~(0x80000 - 1), %eax /* size mask */
+ or $MTRR_PHYS_MASK_VALID, %eax
+ wrmsr
+
+ /* 256 KiB */
+ mov $MTRR_PHYS_BASE(1), %ecx
+ mov $(CONFIG_DCACHE_RAM_BASE + 0x80000), %eax
+ or $MTRR_TYPE_WRBACK, %eax
+ xor %edx,%edx
+ wrmsr
+
+ mov $MTRR_PHYS_MASK(1), %ecx
+ mov $~(0x40000 - 1), %eax /* size mask */
+ or $MTRR_PHYS_MASK_VALID, %eax
+ wrmsr
+#else
/* Configure CAR region as write-back (WB) */
mov $MTRR_PHYS_BASE(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
@@ -82,6 +107,7 @@ clear_var_mtrr:
mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
or $MTRR_PHYS_MASK_VALID, %eax
wrmsr
+#endif
post_code(0x25)
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