[coreboot-gerrit] Patch set updated for coreboot: intel/apollolake: Enable prefetching and caching for BIOS reads
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Thu Jun 23 23:10:28 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15321
-gerrit
commit 235234b336d25767d522d1387aab74d1d2b27fd8
Author: Furquan Shaikh <furquan at google.com>
Date: Wed Jun 22 14:00:09 2016 -0700
intel/apollolake: Enable prefetching and caching for BIOS reads
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/soc/intel/apollolake/include/soc/spi.h | 9 +++++----
src/soc/intel/apollolake/spi.c | 5 +++++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index 20e78d7..cc508e1 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -19,14 +19,15 @@
/* PCI configuration registers */
#define SPIBAR_BIOS_CONTROL 0xdc
+/* Bit definitions for BIOS_CONTROL */
+#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
+#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
+#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
+#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
/* Maximum bytes of data that can fit in FDATAn registers */
#define SPIBAR_FDATA_FIFO_SIZE 0x40
-/* Bit definitions for BIOS_CONTROL */
-#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
-#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
-
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
#define SPIBAR_BIOS_BFPREG 0x00
#define SPIBAR_HSFSTS_CTL 0x04
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 282ed01..7b390bb 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -203,6 +203,11 @@ void spi_init(void)
bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
+
+ /* Enable Prefetching and caching. */
+ bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
+ bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
+
pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
}
More information about the coreboot-gerrit
mailing list