[coreboot-gerrit] Patch set updated for coreboot: spd: Add module voltage for 1.8V
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Thu Jun 23 08:18:15 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15202
-gerrit
commit 3230ddc5e65267d1ab6a78948b5359e5865b6cf9
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Wed Jun 15 19:05:11 2016 +0200
spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in
JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10.
Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/include/spd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/include/spd.h b/src/include/spd.h
index 7aaf4dd..7c4a2e3 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -125,6 +125,7 @@ enum spd_memory_type {
#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
+#define SPD_VOLTAGE_SSTL1 5 /* SSTL 1.8 */
/* SPD_DIMM_CONFIG_TYPE values. */
#define ERROR_SCHEME_NONE 0
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