[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Include _PTS, _WAK and _SWS
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Jun 22 17:34:00 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15138
-gerrit
commit 4cdfd3be2be5fd49f2a152a1d8aeaa99c989c4e3
Author: Hannah Williams <hannah.williams at intel.com>
Date: Wed Jun 8 17:39:37 2016 -0700
soc/intel/apollolake: Include _PTS, _WAK and _SWS
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/apollolake/acpi/globalnvs.asl | 2 ++
src/soc/intel/apollolake/acpi/platform.asl | 20 ++++++++++++++++++++
src/soc/intel/apollolake/include/soc/nvs.h | 14 ++++++++------
3 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 3597788..b2b7f53 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
+ PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl
new file mode 100644
index 0000000..f3202a0
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/platform.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2016 Intel Corp
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <soc/intel/common/acpi/platform.asl>
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index fda3556..c791812 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,13 +28,15 @@
struct global_nvs_t {
/* Miscellaneous */
- uint8_t pcnt; /* 0x00 - Processor Count */
- uint8_t ppcm; /* 0x01 - Max PPC State */
- uint8_t lids; /* 0x02 - LID State */
- uint8_t pwrs; /* 0x03 - AC Power State */
- uint8_t dpte; /* 0x04 - Enable DPTF */
+ uint8_t pcnt; /* 0x00 - Processor Count */
+ uint8_t ppcm; /* 0x01 - Max PPC State */
+ uint8_t lids; /* 0x02 - LID State */
+ uint8_t pwrs; /* 0x03 - AC Power State */
+ uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
- uint8_t unused[247];
+ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
+ uint8_t unused[231];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
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