[coreboot-gerrit] Patch set updated for coreboot: google/reef: Keep ISH enabled for now
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Tue Jun 21 21:57:15 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15142
-gerrit
commit 094c82a7dc9f39958963f4e1146f47588109b636
Author: Furquan Shaikh <furquan at google.com>
Date: Tue Jun 21 11:44:10 2016 -0700
google/reef: Keep ISH enabled for now
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.
BUG=chrome-os-partner:54033
Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/mainboard/google/reef/devicetree.cb | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index e626a4c..d8ddd46 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -6,6 +6,11 @@ chip soc/intel/apollolake
register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
+ # TODO(furquan): Remove this once global reset issue is fixed in later
+ # steppings.
+ # Integrated Sensor Hub
+ register "integrated_sensor_hub_enable" = "1"
+
# EMMC TX DATA Delay 1#
# 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400
# 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200
More information about the coreboot-gerrit
mailing list