[coreboot-gerrit] Patch merged into coreboot/master: intel/apollolake: Enable SPI properly in bootblock and ramstage
gerrit at coreboot.org
gerrit at coreboot.org
Tue Jun 21 19:53:18 CEST 2016
the following patch was just integrated into master:
commit 6ac226d915ade86216d77316c77f824a07dd0e1c
Author: Furquan Shaikh <furquan at google.com>
Date: Wed Jun 15 17:13:20 2016 -0700
intel/apollolake: Enable SPI properly in bootblock and ramstage
Bootblock:
- Temporary BAR needs to be assigned for SPI device until PCI
enumeration is done by ramstage which allocates a new BAR.
- Call spi_init to allow bootblock/verstage to write/erase on flash.
Ramstage:
- spi_init needs to run in ramstage to allow write protect to be
disabled for eventlog and NVRAM updates. This needs to be done pretty
early so that any init calls(e.g. mainboard_ec_init) writing to flash
work properly.
Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.
BUG=chrome-os-partner:54283
Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan at google.com>
Reviewed-on: https://review.coreboot.org/15209
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/15209 for details.
-gerrit
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