[coreboot-gerrit] New patch to review for coreboot: riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler
Jonathan Neuschäfer (j.neuschaefer@gmx.net)
gerrit at coreboot.org
Tue Jun 21 19:45:07 CEST 2016
Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15287
-gerrit
commit dc70376cf782e06dca9fb2589dbcaefedb8d7eec
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date: Tue Jun 21 19:37:03 2016 +0200
riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler
Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
src/arch/riscv/bootblock.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 07d68ab..5092ec0 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -38,10 +38,10 @@ _start:
sd t0, 0(t1)
la t0, exception_handler
- csrw stvec, t0
+ csrw mtvec, t0
# clear any pending interrupts
- csrwi sip, 0
+ csrwi mip, 0
# set up the mstatus register for VM
call mstatus_init
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