[coreboot-gerrit] New patch to review for coreboot: new port: cubietech/cubietruck
Iru Cai (mytbk920423@gmail.com)
gerrit at coreboot.org
Mon Jun 20 16:53:18 CEST 2016
Iru Cai (mytbk920423 at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15264
-gerrit
commit ef9084246d77e8e411d5d17762df2ff525ab277f
Author: Iru Cai <mytbk920423 at gmail.com>
Date: Mon Jun 20 12:02:47 2016 +0800
new port: cubietech/cubietruck
Cubietruck is the third generation of the famous Cubieboard with
Allwinner A20 SoC. This port is based on the Cubieboard port.
Test: Cubietruck runs coreboot and boot to "Oh my! I don't know how to
access CBFS yet.Couldn't load romstage."
Change-Id: I6d2ea3ffbb446bef9a9faa55b2d6e90f0e11ee78
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
---
src/mainboard/cubietech/cubietruck/Kconfig | 29 ++++
src/mainboard/cubietech/cubietruck/Kconfig.name | 2 +
src/mainboard/cubietech/cubietruck/Makefile.inc | 6 +
src/mainboard/cubietech/cubietruck/board_info.txt | 1 +
src/mainboard/cubietech/cubietruck/bootblock.c | 159 ++++++++++++++++++++++
src/mainboard/cubietech/cubietruck/devicetree.cb | 12 ++
src/mainboard/cubietech/cubietruck/memlayout.ld | 31 +++++
src/mainboard/cubietech/cubietruck/romstage.c | 91 +++++++++++++
8 files changed, 331 insertions(+)
diff --git a/src/mainboard/cubietech/cubietruck/Kconfig b/src/mainboard/cubietech/cubietruck/Kconfig
new file mode 100644
index 0000000..6716d52
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/Kconfig
@@ -0,0 +1,29 @@
+if BOARD_CUBIETECH_CUBIETRUCK
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_ALLWINNER_A20
+ select BOARD_ROMSIZE_KB_4096
+ select DRIVER_XPOWERS_AXP209
+
+config MAINBOARD_DIR
+ string
+ default cubietech/cubietruck
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Cubietruck A20"
+
+config MAX_CPUS
+ int
+ default 2
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+config UART_FOR_CONSOLE
+ int
+ default 0
+
+endif # BOARD_CUBIETECH_CUBIETRUCK
diff --git a/src/mainboard/cubietech/cubietruck/Kconfig.name b/src/mainboard/cubietech/cubietruck/Kconfig.name
new file mode 100644
index 0000000..c58def8
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_CUBIETECH_CUBIETRUCK
+ bool "Cubietruck"
diff --git a/src/mainboard/cubietech/cubietruck/Makefile.inc b/src/mainboard/cubietech/cubietruck/Makefile.inc
new file mode 100644
index 0000000..f3a6de2
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/cubietech/cubietruck/board_info.txt b/src/mainboard/cubietech/cubietruck/board_info.txt
new file mode 100644
index 0000000..c67b641
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/board_info.txt
@@ -0,0 +1 @@
+Category: sbc
diff --git a/src/mainboard/cubietech/cubietruck/bootblock.c b/src/mainboard/cubietech/cubietruck/bootblock.c
new file mode 100644
index 0000000..3bc6aba
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/bootblock.c
@@ -0,0 +1,159 @@
+/*
+ * Minimal bootblock for Cubieboard
+ * It sets up CPU clock, and enables the bootblock console.
+ *
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/uart.h>
+#include <console/console.h>
+#include <delay.h>
+#include <cpu/allwinner/a10/gpio.h>
+#include <cpu/allwinner/a10/clock.h>
+#include <cpu/allwinner/a10/dramc.h>
+
+#define CPU_AHB_APB0_DEFAULT \
+ CPU_CLK_SRC_OSC24M \
+ | APB0_DIV_1 \
+ | AHB_DIV_2 \
+ | AXI_DIV_1
+
+#define GPH_STATUS_LEDS ((1 << 7) | (1 << 11) | (1 << 20) | (1 << 21))
+#define GPH_LED1_PIN_NO 21
+#define GPH_LED2_PIN_NO 20
+#define GPH_LED3_PIN_NO 11
+#define GPH_LED4_PIN_NO 7
+
+#define GPB_UART0_FUNC 2
+#define GPB_UART0_PINS ((1 << 22) | (1 << 23))
+
+#define GPC_NAND_FUNC 5
+#define GPC_NAND_PINS 0x0100ffff /* PC0 thru PC15 and PC24 */
+
+#define GPF_SD0_FUNC 2
+#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */
+#define GPH1_SD0_DET_FUNC 5
+
+static void cubieboard_set_sys_clock(void)
+{
+ u32 reg32;
+ struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
+
+ /* Switch CPU clock to main oscillator */
+ write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
+
+ /* Configure the PLL1. The value is the same one used by u-boot
+ * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
+ */
+ write32(&ccm->pll1_cfg, 0xa1005000);
+
+ /* FIXME: Delay to wait for PLL to lock */
+ u32 wait = 1000;
+ while (--wait);
+
+ /* Switch CPU to PLL clock */
+ reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
+ reg32 &= ~CPU_CLK_SRC_MASK;
+ reg32 |= CPU_CLK_SRC_PLL1;
+ write32(&ccm->cpu_ahb_apb0_cfg, reg32);
+
+ setbits_le32(&ccm->ahb_gate0, AHB_GATE_DMA);
+ write32(&ccm->pll6_cfg, 0xa1009911);
+ /* config AHCI */
+ setbits_le32(&ccm->ahb_gate0, AHB_GATE_SATA);
+ setbits_le32(&ccm->pll6_cfg, PLL6_SATA_CLK_EN);
+}
+
+static void cubieboard_setup_clocks(void)
+{
+ struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
+
+ cubieboard_set_sys_clock();
+ /* Configure the clock source for APB1. This drives our UART */
+ write32(&ccm->apb1_clk_div_cfg,
+ APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
+
+ /* Configure the clock for SD0 */
+ write32(&ccm->sd0_clk_cfg,
+ SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
+
+ /* Enable clock to SD0 */
+ a1x_periph_clock_enable(A1X_CLKEN_MMC0);
+}
+
+static void cubieboard_setup_gpios(void)
+{
+ /* Mux Status LED pins */
+ gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT);
+ /* Turn on LED2 to let user know we're executing coreboot code */
+ gpio_set(GPH, GPH_LED2_PIN_NO);
+
+ /* Mux UART pins */
+ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC);
+
+ /* Mux SD pins */
+ gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC);
+ gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC);
+
+ /* Mux NAND pins */
+ gpio_set_multipin_func(GPC, GPC_NAND_PINS, GPC_NAND_FUNC);
+}
+
+static void cubieboard_enable_uart(void)
+{
+ a1x_periph_clock_enable(A1X_CLKEN_UART0);
+}
+
+static void cubietruck_raminit(void)
+{
+ /* parameters copied from u-boot-sunxi */
+ static struct dram_para dram_para = {
+ .clock = 432,
+ .type = 3,
+ .rank_num = 1,
+ .density = 8192,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 2048,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+ };
+
+ dramc_init(&dram_para);
+
+ /* FIXME: ram_check does not compile for ARM,
+ * and we didn't init console yet
+ */
+ ////void *const test_base = (void *)A1X_DRAM_BASE;
+ ////ram_check((u32)test_base, (u32)test_base + 0x1000);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ /* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very
+ * early on to get udelay, which is used almost everywhere else.
+ */
+ init_timer();
+
+ cubieboard_setup_clocks();
+ cubieboard_setup_gpios();
+ cubieboard_enable_uart();
+}
+
+void bootblock_mainboard_init(void)
+{
+ cubietruck_raminit();
+}
diff --git a/src/mainboard/cubietech/cubietruck/devicetree.cb b/src/mainboard/cubietech/cubietruck/devicetree.cb
new file mode 100644
index 0000000..65ea5ff
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/devicetree.cb
@@ -0,0 +1,12 @@
+chip cpu/allwinner/a10
+ device cpu_cluster 0 on end
+
+ chip drivers/xpowers/axp209 # AXP209 is on I²C 0
+ device i2c 0x34 on end
+ register "dcdc2_voltage_mv" = "1400" # Vcore
+ register "dcdc3_voltage_mv" = "1250" # DLL Vdd
+ register "ldo2_voltage_mv" = "3000" # AVCC
+ register "ldo3_voltage_mv" = "2800" # NC?
+ register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8
+ end
+end
diff --git a/src/mainboard/cubietech/cubietruck/memlayout.ld b/src/mainboard/cubietech/cubietruck/memlayout.ld
new file mode 100644
index 0000000..55ba70a
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/memlayout.ld
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+ SRAM_START(0x0)
+ /* eGON.BT0: 32 bytes */
+ BOOTBLOCK(0x20, 0x5fa0)
+ STACK(0x6000, 8K)
+ SRAM_END(0x8000)
+
+ DRAM_START(0x40000000)
+ RAMSTAGE(0x40000000, 16M)
+ ROMSTAGE(0x41000000, 108K)
+}
diff --git a/src/mainboard/cubietech/cubietruck/romstage.c b/src/mainboard/cubietech/cubietruck/romstage.c
new file mode 100644
index 0000000..fa660c8
--- /dev/null
+++ b/src/mainboard/cubietech/cubietruck/romstage.c
@@ -0,0 +1,91 @@
+/*
+ * Basic romstage for Cubieboard
+ *
+ * Set up system voltages, then increase the CPU clock, before turning control
+ * to ramstage. The CPU VDD needs to be properly set before it can run at full
+ * speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot
+ * faster.
+ *
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <cpu/allwinner/a10/clock.h>
+#include <cpu/allwinner/a10/gpio.h>
+#include <cpu/allwinner/a10/twi.h>
+#include <program_loading.h>
+#define __SIMPLE_DEVICE__
+#include <device/device.h>
+#include <drivers/xpowers/axp209/axp209.h>
+#include <drivers/xpowers/axp209/chip.h>
+
+
+#define GPB_TWI0_FUNC 2
+#define GPB_TWI0_PINS ((1 << 0) | (1 << 1))
+
+#define AXP209_BUS 0
+
+static enum cb_err cubieboard_setup_power(void)
+{
+ enum cb_err err;
+ const struct device * pmu;
+ const struct drivers_xpowers_axp209_config *cfg;
+
+ /* Find the AXP209 in devicetree */
+ pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR);
+ if (!pmu) {
+ printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n");
+ return CB_ERR;
+ }
+
+ cfg = pmu->chip_info;
+
+ /* Mux TWI0 pins */
+ gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC);
+ /* Enable TWI0 */
+ a1x_periph_clock_enable(A1X_CLKEN_TWI0);
+ a1x_twi_init(AXP209_BUS, 400000);
+
+ if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) {
+ printk(BIOS_ERR, "PMU initialization failed\n");
+ return err;
+ }
+
+ if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) {
+ printk(BIOS_WARNING, "Power setup incomplete: "
+ "CPU may hang when increasing clock\n");
+ return err;
+ }
+
+ printk(BIOS_SPEW, "VDD CPU (DCDC2): %imv\n", cfg->dcdc2_voltage_mv);
+ printk(BIOS_SPEW, "VDD DLL (DCDC3): %imv\n", cfg->dcdc3_voltage_mv);
+ printk(BIOS_SPEW, "AVCC (LDO2) : %imv\n", cfg->ldo2_voltage_mv);
+ printk(BIOS_SPEW, "CSI1-IO (LDO4) : %imv\n", cfg->ldo4_voltage_mv);
+ printk(BIOS_SPEW, "(LDO3) : %imv\n", cfg->ldo3_voltage_mv);
+
+ return CB_SUCCESS;
+}
+
+void main(void)
+{
+ enum cb_err err;
+
+ console_init();
+
+ /* Configure power rails */
+ err = cubieboard_setup_power();
+
+ if (err == CB_SUCCESS) {
+ /* TODO: Get this clock from devicetree.cb */
+ a1x_set_cpu_clock(1008);
+ } else {
+ /* cubieboard_setup_power() prints more details */
+ printk(BIOS_WARNING, "Will run CPU at reduced speed\n");
+ a1x_set_cpu_clock(384);
+ }
+
+ run_ramstage();
+}
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