[coreboot-gerrit] New patch to review for coreboot: intel/apollolake: Run spi_init in ramstage
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Thu Jun 16 02:25:51 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15209
-gerrit
commit ea318ae2e605a4679987b944536165d419deef99
Author: Furquan Shaikh <furquan at google.com>
Date: Wed Jun 15 17:13:20 2016 -0700
intel/apollolake: Run spi_init in ramstage
spi_init needs to run in ramstage to allow write protect to be disabled
for eventlog and NVRAM updates.
Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.
BUG=chrome-os-partner:54458
Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/soc/intel/apollolake/spi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 469bb9e..3d7059e 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -25,6 +25,7 @@
#include <spi_flash.h>
#include <stdlib.h>
#include <string.h>
+#include <bootstate.h>
/* Helper to create a SPI context on API entry. */
#define BOILERPLATE_CREATE_CTX(ctx) \
@@ -197,6 +198,19 @@ void spi_init(void)
pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
}
+#if ENV_RAMSTAGE
+/*
+ * spi_init() needs to run unconditionally on every boot (including resume) to
+ * allow write protect to be disabled for eventlog and nvram updates.
+ */
+static void spi_init_cb(void *unused)
+{
+ spi_init();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, spi_init_cb, NULL);
+#endif
+
int spi_claim_bus(struct spi_slave *slave)
{
/* There's nothing we need to to here. */
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