[coreboot-gerrit] Patch set updated for coreboot: google/reef: Update flash size to 16MiB
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Thu Jun 16 02:25:32 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15191
-gerrit
commit bc5781322f7ddd1f5e76c7645e6690ff1e7b9412
Author: Furquan Shaikh <furquan at google.com>
Date: Tue Jun 14 17:28:51 2016 -0700
google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.
BUG=chrome-os-partner:54390
Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/mainboard/google/reef/Kconfig | 5 ++---
src/mainboard/google/reef/chromeos.fmd | 16 ++++++++--------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index c1ccc5c..fd948c7 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -3,8 +3,7 @@ if BOARD_GOOGLE_REEF
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_INTEL_APOLLOLAKE
- # FIXME(adurbin): this SPI part is really 16MiB
- select BOARD_ROMSIZE_KB_8192
+ select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
@@ -19,7 +18,7 @@ config BOOT_MEDIA_SPI_BUS
config IFD_BIOS_END
hex
- default 0x77F000
+ default 0xF7F000
config IFD_BIOS_START
hex
diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd
index be87cb4..49f3497 100644
--- a/src/mainboard/google/reef/chromeos.fmd
+++ b/src/mainboard/google/reef/chromeos.fmd
@@ -1,8 +1,8 @@
-FLASH 8M {
- WP_RO at 0x0 0x400000 {
+FLASH 16M {
+ WP_RO at 0x0 0x800000 {
SI_DESC at 0x0 0x1000
IFWI at 0x1000 0x1ff000
- RO_SECTION at 0x200000 0x200000 {
+ RO_SECTION at 0x200000 0x600000 {
RO_VPD at 0x0 0x4000
FMAP at 0x4000 0x800
RO_FRID at 0x4800 0x40
@@ -10,10 +10,10 @@ FLASH 8M {
COREBOOT(CBFS)@0x5000 0x17b000
GBB at 0x180000 0x40000
# logical boot partition 2. Remove with updated CSE
- SIGN_CSE at 0x1c0000 0x10000
+ SIGN_CSE at 0x5c0000 0x10000
}
}
- MISC_RW at 0x400000 0x1a000 {
+ MISC_RW at 0x800000 0x1a000 {
RW_MRC_CACHE at 0x0 0x10000
RW_ELOG at 0x10000 0x4000
RW_SHARED at 0x14000 0x4000 {
@@ -22,16 +22,16 @@ FLASH 8M {
}
RW_VPD at 0x18000 0x2000
}
- RW_SECTION_A at 0x41a000 0x173000 {
+ RW_SECTION_A at 0x81a000 0x173000 {
VBLOCK_A at 0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x162fc0
RW_FWID_A at 0x172fc0 0x40
}
- RW_SECTION_B at 0x58d000 0x173000 {
+ RW_SECTION_B at 0x98d000 0x173000 {
VBLOCK_B at 0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x162fc0
RW_FWID_B at 0x172fc0 0x40
}
- DEVICE_EXTENSION at 0x77f000 0x80000
+ DEVICE_EXTENSION at 0xf7f000 0x80000
}
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