[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add utility functions for Global Reset
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Wed Jun 15 09:08:08 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15198
-gerrit
commit 5cb5963c01563c1e820ef080c314b6ef09319f06
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Tue Jun 14 22:19:14 2016 -0700
soc/intel/apollolake: Add utility functions for Global Reset
Apollolake defines Global Reset, where Host, TXE and PMC are reset.
During boot we may need to trigger a global reset as part of platform
initialization (or for error handling). Define functions to trigger
global reset, enable/disable it and lock global reset enable bit.
Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/include/soc/pm.h | 7 +++++++
src/soc/intel/apollolake/include/soc/reset.h | 29 ++++++++++++++++++++++++++++
src/soc/intel/apollolake/pmutil.c | 24 +++++++++++++++++++++++
src/soc/intel/apollolake/reset.c | 10 +++++++++-
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 856872e..548804c 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -128,6 +128,10 @@
#define GEN_PMCON2 0x1024
# define RPS (1 << 2)
#define GEN_PMCON3 0x1028
+#define ETM 0x1048
+# define CF9_LOCK (1 << 31)
+# define CF9_GLB_RST (1 << 20)
+
/* Generic sleep state types */
#define SLEEP_STATE_S0 0
@@ -168,4 +172,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
+void global_reset_enable(uint8_t enable);
+void global_reset_lock(void);
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/reset.h b/src/soc/intel/apollolake/include/soc/reset.h
new file mode 100644
index 0000000..86174ff
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/reset.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RESET_H
+#define RESET_H
+
+#if CONFIG_HAVE_HARD_RESET
+void hard_reset(void);
+#else
+#define hard_reset() do {} while(0)
+#endif
+void soft_reset(void);
+void cpu_reset(void);
+void global_reset(void);
+
+#endif
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 6e47911..8de2b08 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -365,3 +365,27 @@ int vboot_platform_is_resuming(void)
typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
return typ == SLP_TYP_S3;
}
+
+/* if possible, lock 0xcf9 */
+void global_reset_lock(void)
+{
+ uintptr_t etm = read_pmc_mmio_bar() + ETM;
+ uint32_t reg;
+
+ reg = read32((void *)etm);
+ if (reg & CF9_LOCK)
+ return;
+ reg |= CF9_LOCK;
+ write32((void *)etm, reg);
+}
+
+/* enable or disable global reset */
+void global_reset_enable(uint8_t enable)
+{
+ uintptr_t etm = read_pmc_mmio_bar() + ETM;
+ uint32_t reg;
+
+ reg = read32((void *)etm);
+ reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
+ write32((void *)etm, reg);
+}
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index eb43c41..266d9b3 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -18,7 +18,9 @@
#include <arch/hlt.h>
#include <arch/io.h>
#include <halt.h>
-#include <reset.h>
+#include <soc/reset.h>
+
+#define __SIMPLE_DEVICE__
/* Reset control port */
#define RST_CNT 0xcf9
@@ -48,3 +50,9 @@ void cpu_reset(void)
outb(RST_CPU, RST_CNT);
halt();
}
+
+void global_reset(void)
+{
+ outb(0x6, RST_CNT);
+ halt();
+}
More information about the coreboot-gerrit
mailing list