[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Sat Jun 11 05:36:00 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15157
-gerrit
commit 07219aa4e4f16611ad01e840a6c739e12451e5aa
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Jun 10 21:44:26 2016 -0500
soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()
If a bridge has the primary bus equal to the secondary bus the
busmaster_disable_on_bus() will infinitely call itself. Avoid the
inifinite recursion by checking current bus number against the
secondary bus number.
BUG=chrome-os-partner:54262
TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx
signals which means no more infinite recursion.
Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/common/smihandler.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c
index 0b220e2..5915587 100644
--- a/src/soc/intel/common/smihandler.c
+++ b/src/soc/intel/common/smihandler.c
@@ -104,15 +104,24 @@ static void busmaster_disable_on_bus(int bus)
reg32 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
- /* If this is a bridge, then follow it. */
+ /* If it's not a bridge, move on. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
+ if (hdr != PCI_HEADER_TYPE_BRIDGE &&
+ hdr != PCI_HEADER_TYPE_CARDBUS)
+ continue;
+
+ /*
+ * If secondary bus is equal to current bus bypass
+ * the bridge because it's likely unconfigured and
+ * would cause infinite recursion.
+ */
+ int secbus = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ if (secbus == bus)
+ continue;
+
+ busmaster_disable_on_bus(secbus);
}
}
}
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