[coreboot-gerrit] Patch set updated for coreboot: arch/x86: Enable SSE in bootblock_crt0.S
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Thu Jun 9 17:42:07 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15128
-gerrit
commit 6692f59387bd29eaabbadaa1e56a7236a60eef97
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Wed Jun 8 07:11:48 2016 -0700
arch/x86: Enable SSE in bootblock_crt0.S
Don't write reserved bits in the Quark platform. Follow the previous
boot behavior and just enable SSE.
TEST=Build and run on Galileo Gen2
Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/arch/x86/bootblock_crt0.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 7292b8b..9fbce5d 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -41,14 +41,10 @@ bootblock_protected_mode_entry:
movd %eax, %mm1
movd %edx, %mm2
-#if !IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(CONFIG_SSE)
enable_sse:
- mov %cr0, %eax
- and $~CR0_EM, %ax /* Clear coprocessor emulation CR0.EM */
- or $CR0_MP, %ax /* Set coprocessor monitoring CR0.MP */
- mov %eax, %cr0
mov %cr4, %eax
- or $(CR4_OSFXSR | CR4_OSXMMEXCPT), %ax
+ or $CR4_OSFXSR, %ax
mov %eax, %cr4
#endif /* IS_ENABLED(CONFIG_SSE) */
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