[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Pass serial port address to FSP
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Thu Jun 9 14:53:48 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15079
-gerrit
commit 53aa340654bcce195e375b89f559caa2852f3fd2
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sat Jun 4 16:09:44 2016 -0700
soc/intel/quark: Pass serial port address to FSP
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/romstage/romstage.c | 23 +++++++++++---
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 38 ++++++++++-------------
2 files changed, 34 insertions(+), 27 deletions(-)
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index e27aa68..62f8b21 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -132,6 +132,24 @@ void soc_memory_init_params(struct romstage_params *params,
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
}
+
+ /* Update the UPD data for MemoryInit */
+ printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd);
+ upd->PcdSerialRegisterBase = UART_BASE_ADDRESS;
+ upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+ config->PcdSmmTsegSize : 0;
+}
+
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+ MEMORY_INIT_UPD *new)
+{
+ /* Display the parameters for MemoryInit */
+ printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
+ fsp_display_upd_value("PcdSerialRegisterBase",
+ sizeof(old->PcdSerialRegisterBase),
+ old->PcdSerialRegisterBase, new->PcdSerialRegisterBase);
+ fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize),
+ old->PcdSmmTsegSize, new->PcdSmmTsegSize);
}
void soc_after_ram_init(struct romstage_params *params)
@@ -157,8 +175,3 @@ void soc_after_ram_init(struct romstage_params *params)
/* Initialize the PCIe bridges */
pcie_init();
}
-
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
- MEMORY_INIT_UPD *new)
-{
-}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index ef0cf09..86f5487 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -77,39 +77,39 @@ typedef struct {
typedef struct {
-/** Offset 0x0020
+/** Offset 0x0018
**/
UINT64 Signature;
-/** Offset 0x0028
+/** Offset 0x0020
**/
UINT64 Revision;
-/** Offset 0x0030
+/** Offset 0x0028
**/
UINT32 PcdRmuBinaryBaseAddress;
-/** Offset 0x0034
+/** Offset 0x002C
**/
- UINT32 PcdRmuBinaryLen;
-/** Offset 0x0038
+ UINT32 UnusedUpdSpace0;
+/** Offset 0x0030
**/
- UINT8 PcdSmmTsegSize;
-/** Offset 0x0039
+ UINT32 PcdSerialRegisterBase;
+/** Offset 0x0034
**/
- UINT8 PcdPlatformType;
-/** Offset 0x003A
+ UINT8 PcdSmmTsegSize;
+/** Offset 0x0035
**/
- UINT8 ReservedMemoryInitUpd[22];
+ UINT8 ReservedMemoryInitUpd[3];
} MEMORY_INIT_UPD;
typedef struct {
-/** Offset 0x0050
+/** Offset 0x0038
**/
UINT64 Signature;
-/** Offset 0x0058
+/** Offset 0x0040
**/
UINT64 Revision;
-/** Offset 0x0060
+/** Offset 0x0048
**/
- UINT8 ReservedSiliconInitUpd[32];
+ UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
@@ -131,16 +131,10 @@ typedef struct _UPD_DATA_REGION {
UINT32 SiliconInitUpdOffset;
/** Offset 0x0018
**/
- UINT64 ReservedUpd1;
-/** Offset 0x0020
-**/
MEMORY_INIT_UPD MemoryInitUpd;
-/** Offset 0x0050
+/** Offset 0x0038
**/
SILICON_INIT_UPD SiliconInitUpd;
-/** Offset 0x0080
-**/
- UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
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