[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Configure sd card pins
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Tue Jun 7 21:33:02 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15096
-gerrit
commit 19f4f9f705bee931fc9803bd392b35e079ef1aee
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date: Tue May 31 14:40:45 2016 -0700
mainboard/google/reef: Configure sd card pins
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.
BUG==chrome-os-partner:53747
TEST=verify sd card detection
Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar at intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/gpio.h | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index c429935..506633b 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -52,14 +52,15 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */
/* SDCARD */
- PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
- PAD_CFG_NF(GPIO_173, DN_20K, DEEP, NF1), /* SDCARD_D0 */
- PAD_CFG_NF(GPIO_174, DN_20K, DEEP, NF1), /* SDCARD_D1 */
- PAD_CFG_NF(GPIO_175, DN_20K, DEEP, NF1), /* SDCARD_D2 */
- PAD_CFG_NF(GPIO_176, DN_20K, DEEP, NF1), /* SDCARD_D3 */
- PAD_CFG_NF(GPIO_177, DN_20K, DEEP, NF1), /* SDCARD_CD_N */
- PAD_CFG_NF(GPIO_178, DN_20K, DEEP, NF1), /* SDCARD_CMD */
- PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */
+ PAD_CFG_NF(GPIO_172, NATIVE, DEEP, NF1), /* SDCARD_CLK */
+ PAD_CFG_NF(GPIO_173, NATIVE, DEEP, NF1), /* SDCARD_D0 */
+ PAD_CFG_NF(GPIO_174, NATIVE, DEEP, NF1), /* SDCARD_D1 */
+ PAD_CFG_NF(GPIO_175, NATIVE, DEEP, NF1), /* SDCARD_D2 */
+ PAD_CFG_NF(GPIO_176, NATIVE, DEEP, NF1), /* SDCARD_D3 */
+ PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_N */
+ PAD_CFG_NF(GPIO_178, NATIVE, DEEP, NF1), /* SDCARD_CMD */
+ PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
+ PAD_CFG_NF(GPIO_186, NATIVE, DEEP, NF1), /* SDCARD_LVL_WP */
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */
More information about the coreboot-gerrit
mailing list