[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
Lijian Zhao (lijian.zhao@intel.com)
gerrit at coreboot.org
Tue Jun 7 20:22:23 CEST 2016
Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092
-gerrit
commit 44eb5db2347a10acf86ce68eb219fe33f8869948
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date: Tue May 17 19:26:18 2016 -0700
intel/amenia: Program EMMC dll setting
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.
Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7373
Reviewed-by: Petrov, Andrey <andrey.petrov at intel.com>
Tested-by: Petrov, Andrey <andrey.petrov at intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7586
---
src/mainboard/intel/amenia/devicetree.cb | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index af06848..5f4c6a8 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -1,4 +1,4 @@
-chip soc/intel/apollolake
+6:0chip soc/intel/apollolake
device cpu_cluster 0 on
device lapic 0 on end
@@ -9,6 +9,11 @@ chip soc/intel/apollolake
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
+
+ # EMMC TX DATA Delay 1#
+ # 0x1A[14:8] stands for 26*125 = 3250 psec delay for HS400
+ # 0x1A[6:0] stands for 26*125 = 3250 psec delay for SDR104/HS200
+ register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
device domain 0 on
device pci 00.0 on end # - Host Bridge
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