[coreboot-gerrit] Patch set updated for coreboot: board/intel/amenia: Enable LPSS S0ix
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Fri Jun 3 23:24:33 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056
-gerrit
commit 9daaee628600d4c662af283763cf4fc74649ec7e
Author: Hannah Williams <hannah.williams at intel.com>
Date: Thu Jun 2 15:00:36 2016 -0700
board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS
Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/mainboard/intel/amenia/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index af06848..e4aeeaf 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -10,6 +10,9 @@ chip soc/intel/apollolake
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
+ # LPSS S0ix Enable
+ register "S0ixEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
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