[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Fri Jun 3 23:20:58 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055
-gerrit
commit 70b43dd60061e2b0e22c387046282e3eaa76315c
Author: Saurabh Satija <saurabh.satija at intel.com>
Date: Tue May 3 15:15:31 2016 -0700
soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/apollolake/chip.c | 2 ++
src/soc/intel/apollolake/chip.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index d7c61c1..659686f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -108,6 +108,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
cfg = dev->chip_info;
+ silconfig->S0ixEnable = cfg->S0ixEnable;
+
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 3d9f5bd..4ac5d93 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -45,6 +45,8 @@ struct soc_intel_apollolake_config {
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
+ /* Configure LPSS S0ix Enable */
+ uint8_t S0ixEnable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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