[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: SOC specific c-state table
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Thu Jun 2 05:46:08 CEST 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051
-gerrit
commit 50cd62178499db49083a6a63300e6f979a643181
Author: Hannah Williams <hannah.williams at intel.com>
Date: Mon Apr 18 13:47:08 2016 -0700
soc/apollolake: SOC specific c-state table
Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/apollolake/Kconfig | 1 +
src/soc/intel/apollolake/acpi.c | 35 +++++++++++++++++++++++++++++++++++
src/soc/intel/apollolake/chip.c | 2 ++
3 files changed, 38 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 4643887..52a00d9 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS
select SMM_TSEG
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_SMI
+ select SOC_INTEL_COMMON_ACPI
select SPI_FLASH
select UDELAY_TSC
select TSC_CONSTANT_RATE
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4d610f8..3d3d739 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -26,6 +26,14 @@
#include <soc/pm.h>
#include <soc/nvs.h>
+#define CSTATE_RES(address_space, width, offset, address) \
+ { \
+ .space_id = address_space, \
+ .bit_width = width, \
+ .bit_offset = offset, \
+ .addrl = address, \
+ }
+
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
@@ -157,3 +165,30 @@ void southbridge_inject_dsdt(device_t device)
acpigen_pop_len();
}
}
+static acpi_cstate_t cstate_map[] = {
+ {
+ /* C1 */
+ .ctype = 1, /* ACPI C1 */
+ .latency = 1,
+ .power = 1000,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0),
+ },
+ {
+ .ctype = 2, /* ACPI C2 */
+ .latency = 50,
+ .power = 10,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415),
+ },
+ {
+ .ctype = 3, /* ACPI C3 */
+ .latency = 150,
+ .power = 10,
+ .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419),
+ }
+};
+
+acpi_cstate_t *get_cstate_map(int *entries)
+{
+ *entries = ARRAY_SIZE(cstate_map);
+ return(cstate_map);
+}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f2..a9edbbb 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
@@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = {
.enable_resources = DEVICE_NOOP,
.init = apollolake_init_cpus,
.scan_bus = NULL,
+ .acpi_fill_ssdt_generator = generate_cpu_entries,
};
static void enable_dev(device_t dev)
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