[coreboot-gerrit] New patch to review for coreboot: soc/intel/common: Enable MTRR display during bootblock & postcar

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15990

-gerrit

commit 27863239ca4021b73cd70a23f081f83b6109f2ca
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sat Jul 30 07:17:13 2016 -0700

    soc/intel/common: Enable MTRR display during bootblock & postcar
    
    Update Makefile.inc to allow MTRR display during bootblock and postcar.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/common/Makefile.inc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 429c61c..13ba21b 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -1,5 +1,7 @@
 ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
 
+bootblock-y += util.c
+
 verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
 verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 
@@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 romstage-y += util.c
 romstage-$(CONFIG_MMA) += mma.c
 
+postcar-y += util.c
+
 ramstage-y += hda_verb.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c