[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Handle FspNotify calls

Lee Leahy (leroy.p.leahy@intel.com) gerrit at coreboot.org
Sun Jul 31 02:17:44 CEST 2016


Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15855

-gerrit

commit 833e210ea76023fef2d777f79b8bb99cbd7c3670
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sun Jul 24 18:59:06 2016 -0700

    drivers/intel/fsp2_0: Handle FspNotify calls
    
    Other SOC platforms need to handle the FspNotify calls in the same way
    as Apollo Lake.  Migrate the FspNotify calls into the FSP 2.0 driver.
    Provide a platform callback to handle anything else that needs to be
    done after the FspNotify call.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h |  3 +++
 src/drivers/intel/fsp2_0/notify.c          | 25 +++++++++++++++++++++++++
 src/soc/intel/apollolake/chip.c            | 21 +++------------------
 3 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 1348ead..5a647a2 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -68,6 +68,9 @@ void fsp_notify(enum fsp_notify_phase phase);
 void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
 void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
 
+/* Callback after processing FSP notify */
+void platform_fsp_notify_status(enum fsp_notify_phase phase);
+
 /*
  * # DOCUMENTATION:
  *
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index b002cf8..330c666 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -11,6 +11,7 @@
  */
 
 #include <arch/cpu.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
@@ -53,4 +54,28 @@ void fsp_notify(enum fsp_notify_phase phase)
 	fsp_handle_reset(ret);
 	if (ret != FSP_SUCCESS)
 		die("FspNotify returned an error!\n");
+
+	/* Allow the platform to run something after FspNotify */
+	platform_fsp_notify_status(phase);
+}
+
+static void fsp_notify_dummy(void *arg)
+{
+	enum fsp_notify_phase phase = (uint32_t)arg;
+
+	fsp_notify(phase);
+	if (phase == READY_TO_BOOT)
+		fsp_notify(END_OF_FIRMWARE);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
+						(void *) AFTER_PCI_ENUM);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
+						(void *) READY_TO_BOOT);
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
+						(void *) READY_TO_BOOT);
+
+__attribute__((weak)) void platform_fsp_notify_status(
+	enum fsp_notify_phase phase)
+{
 }
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 812f663..345d7c4 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -406,28 +406,13 @@ struct chip_operations soc_intel_apollolake_ops = {
 	.final = &soc_final
 };
 
-static void fsp_notify_dummy(void *arg)
+void platform_fsp_notify_status(enum fsp_notify_phase phase)
 {
-
-	enum fsp_notify_phase ph = (enum fsp_notify_phase) arg;
-
-	fsp_notify(ph);
-
-	/* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */
-	if (ph == READY_TO_BOOT) {
-		fsp_notify_dummy((void *)END_OF_FIRMWARE);
-		/* Hide the P2SB device to align with previous behavior. */
+	/* Hide the P2SB device to align with previous behavior. */
+	if (phase == END_OF_FIRMWARE)
 		p2sb_hide();
-	}
 }
 
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
-						(void *) AFTER_PCI_ENUM);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
-						(void *) READY_TO_BOOT);
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
-						(void *) READY_TO_BOOT);
-
 /*
  * spi_init() needs to run unconditionally on every boot (including resume) to
  * allow write protect to be disabled for eventlog and nvram updates. This needs



More information about the coreboot-gerrit mailing list