[coreboot-gerrit] Patch set updated for coreboot: WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15454

-gerrit

commit 27b2ef090390fab4f236236a6c97e770510bb105
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Jun 24 18:15:09 2016 -0700

    WIP: soc/intel/apollolake: Update stage link addresses for 768 KiB cache
    
    Update link addresses for romstage and verstage. Also change build time
    relocation address for FSP-M to match.
    
    BUG=chrome-os-partner:51959
    
    Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 3c0b588..dbf7d51 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -142,13 +142,13 @@ config X86_TOP4G_BOOTMEDIA_MAP
 
 config ROMSTAGE_ADDR
 	hex
-	default 0xfef3e000
+	default 0xfef11000
 	help
 	  The base address (in CAR) where romstage should be linked
 
 config VERSTAGE_ADDR
 	hex
-	default 0xfef60000
+	default 0xfef40000
 	help
 	  The base address (in CAR) where verstage should be linked
 
@@ -158,7 +158,7 @@ config CACHE_MRC_SETTINGS
 
 config FSP_M_ADDR
 	hex
-	default 0xfef60000
+	default 0xfef40000
 	help
 	  The address FSP-M will be relocated to during build time