[coreboot-gerrit] Patch set updated for coreboot: google/reef: Enable DPTF in mainboard

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15640

-gerrit

commit 9c96aefe2375345bb3b78c44157f0e918b5568e4
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Tue Jul 12 16:03:29 2016 -0700

    google/reef: Enable DPTF in mainboard
    
    This patch enables DPTF support for Google Reef
    platform, adds the ASL settings specific to Reef
    boards.
    
    BUG=chrome-os-partner:53096
    TEST=Verify that the thermal zones are enumerated
           under /sys/class/thermal in Reef boards. Navigate to
           /sys/class/thermal, and verify that a thermal
           zone of type TCPU exists there.
    
    Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/google/reef/acpi/dptf.asl | 94 +++++++++++++++++++++++++++++++++
 src/mainboard/google/reef/devicetree.cb |  3 ++
 src/mainboard/google/reef/dsdt.asl      |  5 ++
 3 files changed, 102 insertions(+)

diff --git a/src/mainboard/google/reef/acpi/dptf.asl b/src/mainboard/google/reef/acpi/dptf.asl
new file mode 100644
index 0000000..35bbecb
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/dptf.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+#define DPTF_CPU_ACTIVE_AC0	90
+#define DPTF_CPU_ACTIVE_AC1	80
+#define DPTF_CPU_ACTIVE_AC2	70
+#define DPTF_CPU_ACTIVE_AC3	60
+#define DPTF_CPU_ACTIVE_AC4	50
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Battery"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Ambient"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Charger"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		6000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include soc specific DPTF changes */
+#include <soc/intel/apollolake/acpi/dptf.asl>
+/* Include common dptf ASL files */
+#include <soc/intel/common/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index a04a3cd..0763a6d 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -31,6 +31,9 @@ chip soc/intel/apollolake
 	# 0x1C[6:0] stands for 28*125 =  3500 pSec delay for HS200
 	register "emmc_rx_cmd_data_cntl2" = "0x1001C"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route, i.e., if this route changes then the affected GPE
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 7a88fb6..1558182 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -46,4 +46,9 @@ DefinitionBlock(
 
 	/* Mainboard Specific devices */
 	#include "acpi/mainboard.asl"
+
+	Scope (\_SB) {
+		/* Dynamic Platform Thermal Framework */
+		#include "acpi/dptf.asl"
+	}
 }