[coreboot-gerrit] Patch set updated for coreboot: google/reef: Add pull up 20K for LPC SERIRQ

[Kane Chen (kane.chen@intel.com)]

Kane Chen (kane.chen at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15951

-gerrit

commit c967f28e87049eedd63c7a652123916128a8c955
Author: Kane Chen <kane.chen at intel.com>
Date:   Thu Jul 28 19:41:15 2016 +0800

    google/reef: Add pull up 20K for LPC SERIRQ
    
    per hw team's check and info from EDS, this pin needs to be pu 20K.
    Otherwise SoC may not notice interrupt request from
    EC over LPC because SERIRQ line is floating.
    
    BUG=chrome-os-partner:55586
    BRANCH=none
    TEST=boot ok and Quanta factory verified the keyboard issue is gone
    
    Signed-off-by: Kane Chen <kane.chen at intel.com>
    Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a
---
 src/mainboard/google/reef/gpio.h   | 2 +-
 src/soc/intel/apollolake/lpc_lib.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 88f5cdc..1e88215 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP),	 /* SMB_DATA */
 
 	/* LPC */
-	PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */
 	PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
 	PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP),	 /* LPC_CLKOUT1 -- unused */
 	PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),	 /* LPC_AD0 */
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c
index 9428866..7627fea 100644
--- a/src/soc/intel/apollolake/lpc_lib.c
+++ b/src/soc/intel/apollolake/lpc_lib.c
@@ -46,6 +46,7 @@ static const struct lpc_mmio_range {
 };
 
 static const struct pad_config lpc_gpios[] = {
+	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),