[coreboot-gerrit] Patch merged into coreboot/master: intel/apollolake: Add soc specific DPTF values

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5dd2b18540ed5beb272e79820f0d29f88e392b83
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Tue Jul 12 00:42:06 2016 -0700

    intel/apollolake: Add soc specific DPTF values
    
    This patch adds apollolake soc specific change. DPTF
    ASL files are now in src/soc/intel/common so that
    they can be reused but different soc can have different values
    e.g., for skylake cpu soc thermal reporting device is at
    Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
    Function 1. This patch adds a dptf asl file in soc directory where we
    can define all values which can change across soc's and can be
    included in mainboard dptf asl.
    
    BUG=chrome-os-partner:53096
    TEST=In Amenia and Reef board verify that the thermal zones are
           enumerated under /sys/class/thermal in Amenia and Reef board.
           Navigate to /sys/class/thermal, and verify that a thermal
           zone of type TCPU exists there.
    
    Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/15619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See https://review.coreboot.org/15619 for details.

-gerrit