[coreboot-gerrit] Patch set updated for coreboot: src/cpu: Capitalize ROM and RAM
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Thu Jul 28 19:18:34 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15935
-gerrit
commit 2802e66cb1f99c2bcf9a55b6359be6824b1b5a64
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Thu Jul 28 19:15:34 2016 +0200
src/cpu: Capitalize ROM and RAM
Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/cpu/amd/agesa/cache_as_ram.inc | 2 +-
src/cpu/amd/car/post_cache_as_ram.c | 2 +-
src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +-
src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +-
src/cpu/amd/pi/cache_as_ram.inc | 2 +-
src/cpu/intel/haswell/cache_as_ram.inc | 2 +-
src/cpu/intel/haswell/romstage.c | 6 +++---
src/cpu/intel/haswell/stage_cache.c | 2 +-
src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +-
src/cpu/x86/16bit/entry16.inc | 2 +-
src/cpu/x86/16bit/reset16.ld | 2 +-
src/cpu/x86/lapic/lapic_cpu_init.c | 2 +-
12 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 80344ce..293e9a5 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -80,7 +80,7 @@ cache_as_ram_setup:
movl $0xc00000e3, 0x18(%edi)
movl %eax, 0x1c(%edi)
- # load rom based identity mapped page tables
+ # load ROM based identity mapped page tables
mov %ecx, %eax
mov %eax, %cr3
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index ad5a5c7..19aa0a2 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -166,7 +166,7 @@ void post_cache_as_ram(void)
void cache_as_ram_new_stack (void)
{
- print_car_debug("Disabling cache as ram now\n");
+ print_car_debug("Disabling cache as RAM now\n");
disable_cache_as_ram_bsp();
disable_cache();
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index bd9de28..c31b95d 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -171,7 +171,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index cbc5cb8..d48f0e8 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -198,7 +198,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index fd5e66d..40ec1b2 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -81,7 +81,7 @@ cache_as_ram_setup:
movl $0xc00000e3, 0x18(%edi)
movl %eax, 0x1c(%edi)
- # load rom based identity mapped page tables
+ # load ROM based identity mapped page tables
mov %ecx, %eax
mov %eax, %cr3
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 9cdb176..276b9c3 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -145,7 +145,7 @@ clear_mtrrs:
wrmsr
post_code(0x27)
- /* Enable caching for ram init code to run faster */
+ /* Enable caching for RAM init code to run faster */
movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index a05d570..8b62d43 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -113,8 +113,8 @@ static void *setup_romstage_stack_after_car(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. On haswell systems the top of
- * ram under 4GiB is the start of the TSEG region. It is required to
+ /* Cache 8MiB below the top of RAM. On haswell systems the top of
+ * RAM under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
@@ -123,7 +123,7 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Cache 8MiB at the top of ram. Top of ram on haswell systems
+ /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c
index ee945c7..009cc09 100644
--- a/src/cpu/intel/haswell/stage_cache.c
+++ b/src/cpu/intel/haswell/stage_cache.c
@@ -20,7 +20,7 @@
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of ram is defined to be the TSEG base address. */
+ * The top of RAM is defined to be the TSEG base address. */
*size = RESERVED_SMM_SIZE;
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 702881d..6702155 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -147,7 +147,7 @@ clear_mtrrs:
wrmsr
post_code(0x27)
- /* Enable caching for ram init code to run faster */
+ /* Enable caching for RAM init code to run faster */
movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 4c0d323..b4db834 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -95,7 +95,7 @@ _start16bit:
*
* Also load an IDT with NULL limit to prevent the 16bit IDT being used
* in protected mode before c_start.S sets up a 32bit IDT when entering
- * ram stage. In practise: CPU will shutdown on any exception.
+ * RAM stage. In practise: CPU will shutdown on any exception.
* See IA32 manual Vol 3A 19.26 Interrupts.
*/
diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld
index d96755e..e630ce5 100644
--- a/src/cpu/x86/16bit/reset16.ld
+++ b/src/cpu/x86/16bit/reset16.ld
@@ -1,5 +1,5 @@
/*
- * _ROMTOP : The top of the rom used where we
+ * _ROMTOP : The top of the ROM used where we
* need to put the reset vector.
*/
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 1abc28f..ea492dd 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -88,7 +88,7 @@ static void copy_secondary_start_to_lowest_1M(void)
memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
}
- /* copy the _secondary_start to the ram below 1M*/
+ /* copy the _secondary_start to the RAM below 1M*/
memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size);
printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",
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