[coreboot-gerrit] New patch to review for coreboot: Rename __attribute__((packed)) --> __packed
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Jul 27 21:18:57 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15921
-gerrit
commit 6874a1c4d1d99a3b6e4d2fc58318129b6c10cf61
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Wed Jul 27 12:17:07 2016 -0700
Rename __attribute__((packed)) --> __packed
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
Documentation/cbfs.txt | 2 +-
Documentation/timestamp.md | 6 +-
src/arch/x86/gdt.c | 3 +-
src/arch/x86/include/arch/acpi.h | 67 +++++++++++-----------
src/arch/x86/include/arch/pirq_routing.h | 7 ++-
src/arch/x86/include/arch/registers.h | 14 ++---
src/arch/x86/include/arch/smp/mpspec.h | 23 ++++----
src/commonlib/fsp_relocate.c | 3 +-
src/commonlib/include/commonlib/cbfs_serialized.h | 11 ++--
src/commonlib/include/commonlib/fmap_serialized.h | 5 +-
src/commonlib/include/commonlib/rmodule-defs.h | 3 +-
.../include/commonlib/timestamp_serialized.h | 5 +-
src/commonlib/lz4_wrapper.c | 5 +-
src/cpu/allwinner/a10/clock.h | 3 +-
src/cpu/allwinner/a10/gpio.h | 5 +-
src/cpu/allwinner/a10/timer.h | 15 ++---
src/cpu/allwinner/a10/uart.h | 3 +-
src/cpu/intel/smm/gen1/smmrelocate.c | 2 +-
src/cpu/ti/am335x/clock.h | 17 +++---
src/cpu/ti/am335x/gpio.h | 3 +-
src/cpu/ti/am335x/header.c | 3 +-
src/cpu/ti/am335x/header.h | 7 ++-
src/cpu/ti/am335x/uart.h | 4 +-
src/cpu/x86/mp_init.c | 4 +-
src/cpu/x86/pae/pgtbl.c | 6 +-
src/cpu/x86/smm/smm_module_loader.c | 4 +-
src/device/oprom/yabel/device.c | 2 +-
src/device/oprom/yabel/device.h | 6 +-
src/device/oprom/yabel/pmm.h | 2 +-
src/drivers/elog/boot_count.c | 2 +-
src/drivers/elog/elog_internal.h | 6 +-
src/drivers/elog/gsmi.c | 6 +-
src/drivers/i2c/tpm/tpm.h | 14 ++---
src/drivers/intel/fsp1_0/fsp_util.h | 3 +-
src/drivers/intel/fsp1_1/fsp_util.c | 2 +-
src/drivers/intel/fsp1_1/include/fsp/gma.h | 19 +++---
src/drivers/intel/fsp2_0/graphics.c | 2 +-
src/drivers/intel/fsp2_0/hand_off_block.c | 5 +-
.../intel/fsp2_0/header_util/fspupdvpd.spatch | 2 +-
src/drivers/intel/fsp2_0/include/fsp/upd.h | 6 +-
src/drivers/intel/gma/intel_bios.h | 56 +++++++++---------
src/drivers/intel/wifi/wifi.c | 2 +-
src/drivers/siemens/nc_fpga/nc_fpga.h | 4 +-
src/drivers/usb/ehci.h | 6 +-
src/drivers/usb/usb_ch9.h | 2 +-
src/include/compiler.h | 23 ++++++++
src/include/console/spi.h | 7 +--
src/include/cpu/x86/smm.h | 13 +++--
src/include/elog.h | 6 +-
src/include/memory_info.h | 6 +-
src/include/smbios.h | 29 +++++-----
src/include/vbe.h | 7 ++-
src/lib/cbmem_console.c | 3 +-
src/lib/imd.c | 7 ++-
src/lib/tpm2_tlcl_structures.h | 4 +-
src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 2 +-
src/mainboard/siemens/mc_tcu3/ptn3460.h | 5 +-
src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 2 +-
src/mainboard/via/epia-m700/wakeup.c | 4 +-
src/northbridge/amd/amdfam10/amdfam10.h | 8 ++-
src/northbridge/amd/amdk8/f.h | 9 +--
src/northbridge/amd/amdk8/pre_f.h | 5 +-
src/northbridge/amd/amdmct/mct/mct_d.h | 8 +--
src/northbridge/intel/common/mrc_cache.h | 2 +-
src/northbridge/intel/fsp_sandybridge/gma.h | 18 +++---
src/northbridge/intel/haswell/gma.h | 18 +++---
src/northbridge/intel/haswell/haswell.h | 2 +-
src/northbridge/intel/haswell/pei_data.h | 6 +-
src/northbridge/intel/i82830/smihandler.c | 10 ++--
src/northbridge/intel/i945/raminit.h | 2 +-
src/northbridge/intel/nehalem/gma.h | 12 ++--
src/northbridge/intel/nehalem/raminit.c | 4 +-
src/northbridge/intel/sandybridge/gma.h | 14 +++--
src/northbridge/intel/sandybridge/pei_data.h | 2 +-
src/northbridge/intel/sandybridge/raminit.h | 2 +-
src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 14 ++---
src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 8 +--
src/soc/intel/apollolake/include/soc/nvs.h | 2 +-
src/soc/intel/apollolake/include/soc/pm.h | 2 +-
src/soc/intel/baytrail/include/soc/device_nvs.h | 3 +-
src/soc/intel/baytrail/include/soc/efi_wrapper.h | 4 +-
src/soc/intel/baytrail/include/soc/gpio.h | 3 +-
src/soc/intel/baytrail/include/soc/mrc_wrapper.h | 6 +-
src/soc/intel/baytrail/include/soc/nvs.h | 3 +-
src/soc/intel/baytrail/include/soc/pmc.h | 3 +-
src/soc/intel/baytrail/spi.c | 3 +-
src/soc/intel/braswell/include/soc/device_nvs.h | 3 +-
src/soc/intel/braswell/include/soc/gpio.h | 3 +-
src/soc/intel/braswell/include/soc/nvs.h | 3 +-
src/soc/intel/braswell/include/soc/pm.h | 3 +-
src/soc/intel/braswell/spi.c | 3 +-
src/soc/intel/broadwell/include/soc/device_nvs.h | 3 +-
src/soc/intel/broadwell/include/soc/gpio.h | 3 +-
src/soc/intel/broadwell/include/soc/me.h | 51 ++++++++--------
src/soc/intel/broadwell/include/soc/nvs.h | 3 +-
src/soc/intel/broadwell/include/soc/pei_data.h | 7 ++-
src/soc/intel/broadwell/include/soc/smm.h | 3 +-
src/soc/intel/broadwell/spi.c | 3 +-
src/soc/intel/common/gma.h | 19 +++---
src/soc/intel/common/lpss_i2c.c | 2 +-
src/soc/intel/common/mma.c | 2 +-
src/soc/intel/common/mrc_cache.h | 2 +-
.../intel/fsp_baytrail/include/soc/device_nvs.h | 3 +-
src/soc/intel/fsp_baytrail/include/soc/gpio.h | 3 +-
src/soc/intel/fsp_baytrail/include/soc/nvs.h | 3 +-
src/soc/intel/fsp_baytrail/include/soc/pmc.h | 3 +-
src/soc/intel/fsp_baytrail/spi.c | 3 +-
src/soc/intel/fsp_broadwell_de/spi.c | 3 +-
src/soc/intel/quark/include/soc/pei_wrapper.h | 2 +-
src/soc/intel/quark/include/soc/pm.h | 2 +-
src/soc/intel/sch/nvs.h | 2 +-
src/soc/intel/sch/raminit.h | 2 +-
src/soc/intel/skylake/include/soc/device_nvs.h | 3 +-
.../intel/skylake/include/soc/flash_controller.h | 3 +-
src/soc/intel/skylake/include/soc/me.h | 8 ++-
src/soc/intel/skylake/include/soc/nvs.h | 3 +-
src/soc/intel/skylake/include/soc/pei_data.h | 3 +-
src/soc/intel/skylake/include/soc/pm.h | 3 +-
src/soc/intel/skylake/include/soc/smm.h | 3 +-
src/soc/marvell/armada38x/uart.c | 2 +-
src/soc/mediatek/mt8173/uart.c | 5 +-
src/soc/nvidia/tegra124/include/soc/clk_rst.h | 4 +-
src/soc/nvidia/tegra124/include/soc/dma.h | 5 +-
src/soc/nvidia/tegra124/include/soc/emc.h | 3 +-
src/soc/nvidia/tegra124/include/soc/spi.h | 3 +-
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 3 +-
src/soc/nvidia/tegra124/uart.c | 3 +-
src/soc/nvidia/tegra132/include/soc/clk_rst.h | 3 +-
src/soc/nvidia/tegra132/include/soc/clst_clk.h | 3 +-
src/soc/nvidia/tegra132/include/soc/dma.h | 5 +-
src/soc/nvidia/tegra132/include/soc/emc.h | 3 +-
src/soc/nvidia/tegra132/include/soc/spi.h | 3 +-
src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c | 3 +-
src/soc/nvidia/tegra132/uart.c | 3 +-
src/soc/nvidia/tegra210/include/soc/clk_rst.h | 3 +-
src/soc/nvidia/tegra210/include/soc/clst_clk.h | 2 +-
src/soc/nvidia/tegra210/include/soc/dma.h | 5 +-
src/soc/nvidia/tegra210/include/soc/emc.h | 2 +-
src/soc/nvidia/tegra210/include/soc/spi.h | 3 +-
src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 2 +-
src/soc/nvidia/tegra210/uart.c | 2 +-
src/soc/qualcomm/ipq40xx/include/soc/cdp.h | 3 +-
src/soc/qualcomm/ipq40xx/lcc.c | 10 ++--
src/soc/qualcomm/ipq806x/include/soc/cdp.h | 3 +-
src/soc/qualcomm/ipq806x/lcc.c | 11 ++--
src/soc/samsung/exynos5250/i2c.c | 3 +-
src/soc/samsung/exynos5250/include/soc/power.h | 3 +-
src/soc/samsung/exynos5420/i2c.c | 5 +-
src/soc/samsung/exynos5420/include/soc/dmc.h | 7 ++-
src/soc/samsung/exynos5420/include/soc/power.h | 3 +-
src/southbridge/intel/bd82x6x/me.h | 42 +++++++-------
src/southbridge/intel/bd82x6x/nvs.h | 2 +-
src/southbridge/intel/common/gpio.h | 7 ++-
src/southbridge/intel/common/spi.c | 5 +-
src/southbridge/intel/fsp_bd82x6x/gpio.h | 6 +-
src/southbridge/intel/fsp_bd82x6x/me.h | 42 +++++++-------
src/southbridge/intel/fsp_bd82x6x/nvs.h | 2 +-
src/southbridge/intel/fsp_i89xx/gpio.h | 6 +-
src/southbridge/intel/fsp_i89xx/me.h | 42 +++++++-------
src/southbridge/intel/fsp_i89xx/nvs.h | 2 +-
src/southbridge/intel/fsp_rangeley/gpio.h | 4 +-
src/southbridge/intel/fsp_rangeley/nvs.h | 2 +-
src/southbridge/intel/fsp_rangeley/spi.c | 7 ++-
src/southbridge/intel/i82801dx/nvs.h | 2 +-
src/southbridge/intel/i82801gx/nvs.h | 4 +-
src/southbridge/intel/i82801ix/nvs.h | 2 +-
src/southbridge/intel/ibexpeak/me.h | 40 ++++++-------
src/southbridge/intel/ibexpeak/nvs.h | 2 +-
src/southbridge/intel/lynxpoint/lp_gpio.h | 2 +-
src/southbridge/intel/lynxpoint/me.h | 52 +++++++++--------
src/southbridge/intel/lynxpoint/nvs.h | 2 +-
src/southbridge/ricoh/rl5c476/rl5c476.h | 4 +-
src/southbridge/via/vt8237r/nvs.h | 2 +-
src/southbridge/via/vt8237r/vt8237r.h | 4 +-
src/vendorcode/google/chromeos/gnvs.h | 4 +-
src/vendorcode/google/chromeos/vboot_common.h | 3 +-
src/vendorcode/google/chromeos/vpd_tables.h | 15 ++---
util/cbfstool/compiler.h | 23 ++++++++
178 files changed, 726 insertions(+), 555 deletions(-)
diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt
index 7ecc901..76d331d 100644
--- a/Documentation/cbfs.txt
+++ b/Documentation/cbfs.txt
@@ -152,7 +152,7 @@ struct cbfs_header {
u32 offset;
u32 architecture;
u32 pad[1];
-} __attribute__((packed));
+} __packed;
The meaning of each member is as follows:
diff --git a/Documentation/timestamp.md b/Documentation/timestamp.md
index 3a4c73b..821d462 100644
--- a/Documentation/timestamp.md
+++ b/Documentation/timestamp.md
@@ -65,7 +65,7 @@ After such a transition, timestamp_init() must not be run again.
Data structures used
====================
The main structure that maintains information about the timestamp cache is:
-struct __attribute__((__packed__)) timestamp_cache {
+struct __packed timestamp_cache {
uint16_t cache_state;
struct timestamp_table table;
struct timestamp_entry entries[MAX_TIMESTAMP_CACHE];
@@ -109,7 +109,7 @@ struct timestamp_table {
uint32_t max_entries;
uint32_t num_entries;
struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
+} __packed;
It indicates the base time for all timestamp entries, maximum number
of entries that can be stored, total number of entries that currently
@@ -125,7 +125,7 @@ defined by:
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
-} __attribute__((packed));
+} __packed;
entry_id holds the timestamp id corresponding to this entry and
entry_stamp holds the actual timestamp.
diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c
index fe14155..3d36085 100644
--- a/src/arch/x86/gdt.c
+++ b/src/arch/x86/gdt.c
@@ -15,6 +15,7 @@
#include <types.h>
#include <string.h>
+#include <compiler.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/gdt.h>
@@ -27,7 +28,7 @@ struct gdtarg {
#else
u32 base;
#endif
-} __attribute__((packed));
+} __packed;
/* Copy GDT to new location and reload it.
* FIXME: We only do this for BSP CPU.
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index dfbffb3..0ef6a45 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -49,6 +49,7 @@
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#include <stdint.h>
#include <rules.h>
+#include <compiler.h>
#include <commonlib/helpers.h>
#include <device/device.h>
@@ -68,7 +69,7 @@ typedef struct acpi_rsdp {
u64 xsdt_address; /* Physical address of XSDT (64 bits) */
u8 ext_checksum; /* Checksum of the whole table */
u8 reserved[3];
-} __attribute__ ((packed)) acpi_rsdp_t;
+} __packed acpi_rsdp_t;
/* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum. */
/* GAS (Generic Address Structure) */
@@ -82,7 +83,7 @@ typedef struct acpi_gen_regaddr {
};
u32 addrl; /* Register address, low 32 bits */
u32 addrh; /* Register address, high 32 bits */
-} __attribute__ ((packed)) acpi_addr_t;
+} __packed acpi_addr_t;
#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */
#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */
@@ -118,7 +119,7 @@ typedef struct acpi_table_header {
u32 oem_revision; /* OEM revision number */
char asl_compiler_id[4]; /* ASL compiler vendor ID */
u32 asl_compiler_revision; /* ASL compiler revision number */
-} __attribute__ ((packed)) acpi_header_t;
+} __packed acpi_header_t;
/* A maximum number of 32 ACPI tables ought to be enough for now. */
#define MAX_ACPI_TABLES 32
@@ -127,13 +128,13 @@ typedef struct acpi_table_header {
typedef struct acpi_rsdt {
struct acpi_table_header header;
u32 entry[MAX_ACPI_TABLES];
-} __attribute__ ((packed)) acpi_rsdt_t;
+} __packed acpi_rsdt_t;
/* XSDT (Extended System Description Table) */
typedef struct acpi_xsdt {
struct acpi_table_header header;
u64 entry[MAX_ACPI_TABLES];
-} __attribute__ ((packed)) acpi_xsdt_t;
+} __packed acpi_xsdt_t;
/* HPET timers */
typedef struct acpi_hpet {
@@ -143,20 +144,20 @@ typedef struct acpi_hpet {
u8 number;
u16 min_tick;
u8 attributes;
-} __attribute__ ((packed)) acpi_hpet_t;
+} __packed acpi_hpet_t;
/* MCFG (PCI Express MMIO config space BAR description table) */
typedef struct acpi_mcfg {
struct acpi_table_header header;
u8 reserved[8];
-} __attribute__ ((packed)) acpi_mcfg_t;
+} __packed acpi_mcfg_t;
typedef struct acpi_tcpa {
struct acpi_table_header header;
u16 platform_class;
u32 laml;
u64 lasa;
-} __attribute__ ((packed)) acpi_tcpa_t;
+} __packed acpi_tcpa_t;
typedef struct acpi_mcfg_mmconfig {
u32 base_address;
@@ -165,7 +166,7 @@ typedef struct acpi_mcfg_mmconfig {
u8 start_bus_number;
u8 end_bus_number;
u8 reserved[4];
-} __attribute__ ((packed)) acpi_mcfg_mmconfig_t;
+} __packed acpi_mcfg_mmconfig_t;
/* SRAT (System Resource Affinity Table) */
typedef struct acpi_srat {
@@ -173,7 +174,7 @@ typedef struct acpi_srat {
u32 resv;
u64 resv1;
/* Followed by static resource allocation structure[n] */
-} __attribute__ ((packed)) acpi_srat_t;
+} __packed acpi_srat_t;
/* SRAT: Processor Local APIC/SAPIC Affinity Structure */
typedef struct acpi_srat_lapic {
@@ -185,7 +186,7 @@ typedef struct acpi_srat_lapic {
u8 local_sapic_eid; /* Local SAPIC EID */
u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */
u32 resv; /* TODO: Clock domain in ACPI 4.0. */
-} __attribute__ ((packed)) acpi_srat_lapic_t;
+} __packed acpi_srat_lapic_t;
/* SRAT: Memory Affinity Structure */
typedef struct acpi_srat_mem {
@@ -200,23 +201,23 @@ typedef struct acpi_srat_mem {
u32 resv1;
u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, other bits reserved to 0 */
u32 resv2[2];
-} __attribute__ ((packed)) acpi_srat_mem_t;
+} __packed acpi_srat_mem_t;
/* SLIT (System Locality Distance Information Table) */
typedef struct acpi_slit {
struct acpi_table_header header;
/* Followed by static resource allocation 8+byte[num*num] */
-} __attribute__ ((packed)) acpi_slit_t;
+} __packed acpi_slit_t;
/* MADT (Multiple APIC Description Table) */
typedef struct acpi_madt {
struct acpi_table_header header;
u32 lapic_addr; /* Local APIC address */
u32 flags; /* Multiple APIC flags */
-} __attribute__ ((packed)) acpi_madt_t;
+} __packed acpi_madt_t;
typedef struct acpi_ivrs_info {
-} __attribute__ ((packed)) acpi_ivrs_info_t;
+} __packed acpi_ivrs_info_t;
/* IVRS IVHD (I/O Virtualization Hardware Definition Block) */
typedef struct acpi_ivrs_ivhd {
@@ -231,7 +232,7 @@ typedef struct acpi_ivrs_ivhd {
uint16_t iommu_info;
uint32_t efr;
uint8_t entry[0];
-} __attribute__ ((packed)) acpi_ivrs_ivhd_t;
+} __packed acpi_ivrs_ivhd_t;
/* IVRS (I/O Virtualization Reporting Structure) */
typedef struct acpi_ivrs {
@@ -239,7 +240,7 @@ typedef struct acpi_ivrs {
uint32_t iv_info;
uint32_t reserved[2];
struct acpi_ivrs_ivhd ivhd;
-} __attribute__ ((packed)) acpi_ivrs_t;
+} __packed acpi_ivrs_t;
enum dev_scope_type {
SCOPE_PCI_ENDPOINT = 1,
@@ -257,8 +258,8 @@ typedef struct dev_scope {
struct {
u8 dev;
u8 fn;
- } __attribute__((packed)) path[0];
-} __attribute__ ((packed)) dev_scope_t;
+ } __packed path[0];
+} __packed dev_scope_t;
enum dmar_type {
DMAR_DRHD = 0,
@@ -283,7 +284,7 @@ typedef struct dmar_entry {
u8 reserved;
u16 segment;
u64 bar;
-} __attribute__ ((packed)) dmar_entry_t;
+} __packed dmar_entry_t;
/* DMAR (DMA Remapping Reporting Structure) */
typedef struct acpi_dmar {
@@ -292,7 +293,7 @@ typedef struct acpi_dmar {
u8 flags;
u8 reserved[10];
dmar_entry_t structure[0];
-} __attribute__ ((packed)) acpi_dmar_t;
+} __packed acpi_dmar_t;
/* MADT: APIC Structure Types */
/* TODO: Convert to ALLCAPS. */
@@ -319,7 +320,7 @@ typedef struct acpi_madt_lapic {
u8 processor_id; /* ACPI processor ID */
u8 apic_id; /* Local APIC ID */
u32 flags; /* Local APIC flags */
-} __attribute__ ((packed)) acpi_madt_lapic_t;
+} __packed acpi_madt_lapic_t;
/* MADT: Local APIC NMI Structure */
typedef struct acpi_madt_lapic_nmi {
@@ -328,7 +329,7 @@ typedef struct acpi_madt_lapic_nmi {
u8 processor_id; /* ACPI processor ID */
u16 flags; /* MPS INTI flags */
u8 lint; /* Local APIC LINT# */
-} __attribute__ ((packed)) acpi_madt_lapic_nmi_t;
+} __packed acpi_madt_lapic_nmi_t;
/* MADT: I/O APIC Structure */
typedef struct acpi_madt_ioapic {
@@ -338,7 +339,7 @@ typedef struct acpi_madt_ioapic {
u8 reserved;
u32 ioapic_addr; /* I/O APIC address */
u32 gsi_base; /* Global system interrupt base */
-} __attribute__ ((packed)) acpi_madt_ioapic_t;
+} __packed acpi_madt_ioapic_t;
/* MADT: Interrupt Source Override Structure */
typedef struct acpi_madt_irqoverride {
@@ -348,7 +349,7 @@ typedef struct acpi_madt_irqoverride {
u8 source; /* Bus-relative int. source (IRQ) */
u32 gsirq; /* Global system interrupt */
u16 flags; /* MPS INTI flags */
-} __attribute__ ((packed)) acpi_madt_irqoverride_t;
+} __packed acpi_madt_irqoverride_t;
/* FADT (Fixed ACPI Description Table) */
typedef struct acpi_fadt {
@@ -408,7 +409,7 @@ typedef struct acpi_fadt {
struct acpi_gen_regaddr x_pm_tmr_blk;
struct acpi_gen_regaddr x_gpe0_blk;
struct acpi_gen_regaddr x_gpe1_blk;
-} __attribute__ ((packed)) acpi_fadt_t;
+} __packed acpi_fadt_t;
/* FADT TABLE Revision values */
#define ACPI_FADT_REV_ACPI_1_0 1
@@ -480,7 +481,7 @@ typedef struct acpi_facs {
u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
u8 version; /* ACPI 4.0: 2 */
u8 resv[31]; /* FIXME: 4.0: ospm_flags */
-} __attribute__ ((packed)) acpi_facs_t;
+} __packed acpi_facs_t;
/* FACS flags */
#define ACPI_FACS_S4BIOS_F (1 << 0)
@@ -495,14 +496,14 @@ typedef struct acpi_ecdt {
u32 uid; /* UID */
u8 gpe_bit; /* GPE bit */
u8 ec_id[]; /* EC ID */
-} __attribute__ ((packed)) acpi_ecdt_t;
+} __packed acpi_ecdt_t;
/* HEST (Hardware Error Source Table) */
typedef struct acpi_hest {
struct acpi_table_header header;
u32 error_source_count;
/* error_source_struct(s) */
-} __attribute__ ((packed)) acpi_hest_t;
+} __packed acpi_hest_t;
/* Error Source Descriptors */
typedef struct acpi_hest_esd {
@@ -513,7 +514,7 @@ typedef struct acpi_hest_esd {
u8 enabled;
u32 prealloc_erecords; /* The number of error records to pre-allocate for this error source. */
u32 max_section_per_record;
-} __attribute__ ((packed)) acpi_hest_esd_t;
+} __packed acpi_hest_esd_t;
/* Hardware Error Notification */
typedef struct acpi_hest_hen {
@@ -526,14 +527,14 @@ typedef struct acpi_hest_hen {
u32 sw2poll_threshold_win;
u32 error_threshold_val;
u32 error_threshold_win;
-} __attribute__ ((packed)) acpi_hest_hen_t;
+} __packed acpi_hest_hen_t;
typedef struct acpi_cstate {
u8 ctype;
u16 latency;
u32 power;
acpi_addr_t resource;
-} __attribute__ ((packed)) acpi_cstate_t;
+} __packed acpi_cstate_t;
typedef struct acpi_tstate {
u32 percent;
@@ -541,7 +542,7 @@ typedef struct acpi_tstate {
u32 latency;
u32 control;
u32 status;
-} __attribute__ ((packed)) acpi_tstate_t;
+} __packed acpi_tstate_t;
unsigned long fw_cfg_acpi_tables(unsigned long start);
diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
index d1390ba..249db91 100644
--- a/src/arch/x86/include/arch/pirq_routing.h
+++ b/src/arch/x86/include/arch/pirq_routing.h
@@ -29,6 +29,7 @@
#if CONFIG_GENERATE_PIRQ_TABLE
#include <stdint.h>
+#include <compiler.h>
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
#define PIRQ_VERSION 0x0100
@@ -38,10 +39,10 @@ struct irq_info {
struct {
u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
u16 bitmap; /* Available IRQs */
- } __attribute__((packed)) irq[4];
+ } __packed irq[4];
u8 slot; /* Slot number, 0=onboard */
u8 rfu;
-} __attribute__((packed));
+} __packed;
struct irq_routing_table {
u32 signature; /* PIRQ_SIGNATURE should be here */
@@ -54,7 +55,7 @@ struct irq_routing_table {
u8 rfu[11];
u8 checksum; /* Modulo 256 checksum must give zero */
struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
-} __attribute__((packed));
+} __packed;
unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table);
unsigned long write_pirq_routing_table(unsigned long start);
diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h
index 2ffcafb..76fda28 100644
--- a/src/arch/x86/include/arch/registers.h
+++ b/src/arch/x86/include/arch/registers.h
@@ -16,7 +16,7 @@
#ifndef __ARCH_REGISTERS_H
#define __ARCH_REGISTERS_H
-#define __PACKED __attribute__((packed))
+#include <compiler.h>
#define DOWNTO8(A) \
union { \
@@ -25,22 +25,22 @@
struct { \
uint8_t A##l; \
uint8_t A##h; \
- } __PACKED; \
+ } __packed; \
uint16_t A##x; \
- } __PACKED; \
+ } __packed; \
uint16_t h##A##x; \
- } __PACKED; \
+ } __packed; \
uint32_t e##A##x; \
- } __PACKED;
+ } __packed;
#define DOWNTO16(A) \
union { \
struct { \
uint16_t A; \
uint16_t h##A; \
- } __PACKED; \
+ } __packed; \
uint32_t e##A; \
- } __PACKED;
+ } __packed;
struct eregs {
DOWNTO8(a);
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 28a3e11..62746be 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -16,6 +16,7 @@
#ifndef __ASM_MPSPEC_H
#define __ASM_MPSPEC_H
+#include <compiler.h>
#include <device/device.h>
#include <cpu/x86/lapic_def.h>
@@ -53,7 +54,7 @@ struct intel_mp_floating
u8 mpf_feature3; /* Unused (0) */
u8 mpf_feature4; /* Unused (0) */
u8 mpf_feature5; /* Unused (0) */
-} __attribute__((packed));
+} __packed;
struct mp_config_table
{
@@ -71,7 +72,7 @@ struct mp_config_table
u16 mpe_length; /* Extended Table size */
u8 mpe_checksum; /* Extended Table checksum */
u8 reserved;
-} __attribute__((packed));
+} __packed;
/* Followed by entries */
@@ -95,14 +96,14 @@ struct mpc_config_processor
#define MPC_CPU_FAMILY_MASK 0xF00
u32 mpc_featureflag; /* CPUID feature value */
u32 mpc_reserved[2];
-} __attribute__((packed));
+} __packed;
struct mpc_config_bus
{
u8 mpc_type;
u8 mpc_busid;
u8 mpc_bustype[6];
-} __attribute__((packed));
+} __packed;
#define BUSTYPE_EISA "EISA"
#define BUSTYPE_ISA "ISA"
@@ -120,7 +121,7 @@ struct mpc_config_ioapic
u8 mpc_flags;
#define MPC_APIC_USABLE 0x01
void *mpc_apicaddr;
-} __attribute__((packed));
+} __packed;
struct mpc_config_intsrc
{
@@ -131,7 +132,7 @@ struct mpc_config_intsrc
u8 mpc_srcbusirq;
u8 mpc_dstapic;
u8 mpc_dstirq;
-} __attribute__((packed));
+} __packed;
enum mp_irq_source_types {
mp_INT = 0,
@@ -160,7 +161,7 @@ struct mpc_config_lintsrc
u8 mpc_destapic;
#define MP_APIC_ALL 0xFF
u8 mpc_destapiclint;
-} __attribute__((packed));
+} __packed;
/*
* Default configurations
@@ -192,7 +193,7 @@ enum mp_bustype {
struct mp_exten_config {
u8 mpe_type;
u8 mpe_length;
-} __attribute__((packed));
+} __packed;
typedef struct mp_exten_config *mpe_t;
@@ -208,7 +209,7 @@ struct mp_exten_system_address_space {
u32 mpe_address_base_high;
u32 mpe_address_length_low;
u32 mpe_address_length_high;
-} __attribute__((packed));
+} __packed;
struct mp_exten_bus_hierarchy {
u8 mpe_type;
@@ -218,7 +219,7 @@ struct mp_exten_bus_hierarchy {
#define BUS_SUBTRACTIVE_DECODE 1
u8 mpe_parent_busid;
u8 reserved[3];
-} __attribute__((packed));
+} __packed;
struct mp_exten_compatibility_address_space {
u8 mpe_type;
@@ -244,7 +245,7 @@ struct mp_exten_compatibility_address_space {
* XFB0 - XFBB
* XFC0 - XCDF
*/
-} __attribute__((packed));
+} __packed;
void mptable_init(struct mp_config_table *mc, u32 lapic_addr);
void *smp_next_mpc_entry(struct mp_config_table *mc);
diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c
index 7f1e49a..c90eeeb 100644
--- a/src/commonlib/fsp_relocate.c
+++ b/src/commonlib/fsp_relocate.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <console/console.h>
#include <commonlib/endian.h>
#include <commonlib/fsp.h>
@@ -67,7 +68,7 @@ struct fsp_patch_table {
uint8_t reserved;
uint32_t patch_entry_num;
uint32_t patch_entries[0];
-} __attribute__((packed));
+} __packed;
#define FSPP_SIG 0x50505346
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
index c01ba1a..e117dc2 100644
--- a/src/commonlib/include/commonlib/cbfs_serialized.h
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -48,6 +48,7 @@
#define _CBFS_SERIALIZED_H_
#include <stdint.h>
+#include <compiler.h>
/** These are standard values for the known compression
algorithms that coreboot knows about for stages and
@@ -100,7 +101,7 @@ struct cbfs_header {
uint32_t offset;
uint32_t architecture;
uint32_t pad[1];
-} __attribute__((packed));
+} __packed;
/* this used to be flexible, but wasn't ever set to something different. */
#define CBFS_ALIGNMENT 64
@@ -135,7 +136,7 @@ struct cbfs_file {
uint32_t type;
uint32_t checksum;
uint32_t offset;
-} __attribute__((packed));
+} __packed;
/*
* ROMCC does not understand uint64_t, so we hide future definitions as they are
@@ -157,7 +158,7 @@ struct cbfs_stage {
uint64_t load; /** Where to load in memory */
uint32_t len; /** length of data to load */
uint32_t memlen; /** total length of object in memory */
-} __attribute__((packed));
+} __packed;
/** this is the sub-header for payload components. Payloads
are loaded by coreboot at the end of the boot process */
@@ -169,7 +170,7 @@ struct cbfs_payload_segment {
uint64_t load_addr;
uint32_t len;
uint32_t mem_len;
-} __attribute__((packed));
+} __packed;
struct cbfs_payload {
struct cbfs_payload_segment segments;
@@ -184,7 +185,7 @@ struct cbfs_payload {
struct cbfs_optionrom {
uint32_t compression;
uint32_t len;
-} __attribute__((packed));
+} __packed;
#endif /* __ROMCC__ */
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
index 3585f0b..cea231b 100644
--- a/src/commonlib/include/commonlib/fmap_serialized.h
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -37,6 +37,7 @@
#define FLASHMAP_SERIALIZED_H__
#include <stdint.h>
+#include <compiler.h>
#define FMAP_SIGNATURE "__FMAP__"
#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
@@ -56,7 +57,7 @@ struct fmap_area {
uint32_t size; /* size in bytes */
uint8_t name[FMAP_STRLEN]; /* descriptive name */
uint16_t flags; /* flags for this area */
-} __attribute__((packed));
+} __packed;
struct fmap {
uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
@@ -68,6 +69,6 @@ struct fmap {
uint16_t nareas; /* number of areas described by
fmap_areas[] below */
struct fmap_area areas[];
-} __attribute__((packed));
+} __packed;
#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
index 0922c81..485d638 100644
--- a/src/commonlib/include/commonlib/rmodule-defs.h
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <stddef.h>
+#include <compiler.h>
#define RMODULE_MAGIC 0xf8fe
#define RMODULE_VERSION_1 1
@@ -54,6 +55,6 @@ struct rmodule_header {
uint32_t bss_end;
/* Add some room for growth. */
uint32_t padding[4];
-} __attribute__ ((packed));
+} __packed;
#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index aec93c4..38337d6 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -17,11 +17,12 @@
#define __TIMESTAMP_SERIALIZED_H__
#include <stdint.h>
+#include <compiler.h>
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
-} __attribute__((packed));
+} __packed;
struct timestamp_table {
uint64_t base_time;
@@ -29,7 +30,7 @@ struct timestamp_table {
uint16_t tick_freq_mhz;
uint32_t num_entries;
struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
+} __packed;
enum timestamp_id {
TS_START_ROMSTAGE = 1,
diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index 0342868..2803d12 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -34,6 +34,7 @@
#include <commonlib/helpers.h>
#include <stdint.h>
#include <string.h>
+#include <compiler.h>
/* LZ4 comes with its own supposedly portable memory access functions, but they
* seem to be very inefficient in practice (at least on ARM64). Since coreboot
@@ -115,7 +116,7 @@ struct lz4_frame_header {
};
/* + uint64_t content_size iff has_content_size is set */
/* + uint8_t header_checksum */
-} __attribute__((packed));
+} __packed;
struct lz4_block_header {
union {
@@ -127,7 +128,7 @@ struct lz4_block_header {
};
/* + size bytes of data */
/* + uint32_t block_checksum iff has_block_checksum is set */
-} __attribute__((packed));
+} __packed;
size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
{
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h
index d1729a3..021cb29 100644
--- a/src/cpu/allwinner/a10/clock.h
+++ b/src/cpu/allwinner/a10/clock.h
@@ -23,6 +23,7 @@
#include "memmap.h"
#include <types.h>
+#include <compiler.h>
/* CPU_AHB_APB0 config values */
#define CPU_CLK_SRC_MASK (3 << 16)
@@ -267,7 +268,7 @@ struct a10_ccm {
u32 mali_clk_cfg; /* 0x154 */
u8 res7[0x4];
u32 mbus_clk_cfg; /* 0x15c */
-} __attribute__ ((packed));
+} __packed;
void a1x_periph_clock_enable(enum a1x_clken periph);
void a1x_periph_clock_disable(enum a1x_clken periph);
diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h
index 8d95074..a126801 100644
--- a/src/cpu/allwinner/a10/gpio.h
+++ b/src/cpu/allwinner/a10/gpio.h
@@ -19,6 +19,7 @@
#define __CPU_ALLWINNER_A10_PINMUX_H
#include <types.h>
+#include <compiler.h>
#define GPIO_BASE 0x01C20800
@@ -42,7 +43,7 @@ struct a10_gpio_port {
u32 dat;
u32 drv[2];
u32 pul[2];
-} __attribute__ ((packed));
+} __packed;
struct a10_gpio {
struct a10_gpio_port port[10];
@@ -58,7 +59,7 @@ struct a10_gpio {
u32 sdr_pad_drv;
u32 sdr_pad_pul;
-} __attribute__ ((packed));
+} __packed;
/* gpio.c */
void gpio_set(u8 port, u8 pin);
diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h
index 7e10f2f..e24bf66 100644
--- a/src/cpu/allwinner/a10/timer.h
+++ b/src/cpu/allwinner/a10/timer.h
@@ -23,6 +23,7 @@
#include "memmap.h"
#include <types.h>
+#include <compiler.h>
/* TMRx_CTRL values */
#define TIMER_CTRL_MODE_SINGLE (1 << 7)
@@ -48,7 +49,7 @@ struct a1x_timer {
u32 interval;
u32 val;
u8 res[4];
-} __attribute__ ((packed));
+} __packed;
/* Audio video sync*/
struct a1x_avs {
@@ -56,27 +57,27 @@ struct a1x_avs {
u32 cnt0; /* 0x84 */
u32 cnt1; /* 0x88 */
u32 div; /* 0x8c */
-} __attribute__ ((packed));
+} __packed;
/* Watchdog */
struct a1x_wdog {
u32 ctrl; /* 0x90 */
u32 mode; /* 0x94 */
-} __attribute__ ((packed));
+} __packed;
/* 64 bit counter */
struct a1x_64cnt {
u32 ctrl; /* 0xa0 */
u32 lo; /* 0xa4 */
u32 hi; /* 0xa8 */
-} __attribute__ ((packed));
+} __packed;
/* Rtc */
struct a1x_rtc {
u32 ctrl; /* 0x100 */
u32 yymmdd; /* 0x104 */
u32 hhmmss; /* 0x108 */
-} __attribute__ ((packed));
+} __packed;
/* Alarm */
struct a1x_alarm {
@@ -85,7 +86,7 @@ struct a1x_alarm {
u32 en; /* 0x114 */
u32 irq_en; /* 0x118 */
u32 irq_sta; /* 0x11c */
-} __attribute__ ((packed));
+} __packed;
struct a1x_timer_module {
u32 irq_en; /* 0x00 */
@@ -103,7 +104,7 @@ struct a1x_timer_module {
u32 gp_data[4];
u8 res5[8];
u32 cpu_cfg;
-} __attribute__ ((packed));
+} __packed;
u8 a1x_get_cpu_chip_revision(void);
diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h
index a5ed2a9..92a87e5 100644
--- a/src/cpu/allwinner/a10/uart.h
+++ b/src/cpu/allwinner/a10/uart.h
@@ -26,6 +26,7 @@
#define CPU_ALLWINNER_A10_UART_H
#include <types.h>
+#include <compiler.h>
struct a10_uart {
union {
@@ -71,7 +72,7 @@ struct a10_uart {
u8 reserved_0xa0[4];
u32 halt; /* Halt register */
-} __attribute__ ((packed));
+} __packed;
enum uart_parity {
UART_PARITY_NONE,
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 06b140e..3f4b5d9 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -40,7 +40,7 @@ struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
struct smm_relocation_params {
diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h
index c1f1926..564838a 100644
--- a/src/cpu/ti/am335x/clock.h
+++ b/src/cpu/ti/am335x/clock.h
@@ -16,6 +16,7 @@
#define __CPU_TI_AM335X_CLOCK_H__
#include <stdint.h>
+#include <compiler.h>
enum {
CM_ST_NO_SLEEP = 0x0,
@@ -106,7 +107,7 @@ struct am335x_cm_per_regs {
uint32_t lcdc_st; // 0x148
uint32_t clkdiv32k; // 0x14c
uint32_t clk_24mhz_st; // 0x150
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000;
/* Clock module wakeup registers */
@@ -166,7 +167,7 @@ struct am335x_cm_wkup_regs {
uint8_t _rsv0[4]; // 0xd0-0xd3
uint32_t wkup_wdt1; // 0xd4
uint32_t div_m6_dpll_core; // 0xd8
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400;
/* Clock module pll registers */
@@ -187,20 +188,20 @@ struct am335x_cm_dpll_regs {
uint32_t clksel_lcdc_pixel_clk; // 0x34
uint32_t clksel_wdt1_clk; // 0x38
uint32_t clksel_gpio0_dbclk; // 0x3c
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500;
/* Clock module mpu registers */
struct am335x_cm_mpu_regs {
uint32_t st; // 0x0
uint32_t mpu; // 0x4
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600;
/* Clock module device registers */
struct am335x_cm_device_regs {
uint32_t cm_clkout_ctrl; // 0x0
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_device_regs * const am335x_cm_device =
(void *)0x44e00700;
@@ -208,7 +209,7 @@ static struct am335x_cm_device_regs * const am335x_cm_device =
struct am335x_cm_rtc_regs {
uint32_t rtc; // 0x0
uint32_t st; // 0x4
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800;
/* Clock module graphics controller registers */
@@ -219,7 +220,7 @@ struct am335x_cm_gfx_regs {
uint32_t l4ls_gfx_st; // 0xc
uint32_t mmucfg; // 0x10
uint32_t mmudata; // 0x14
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900;
/* Clock module efuse registers */
@@ -227,7 +228,7 @@ struct am335x_cm_cefuse_regs {
uint32_t st; // 0x0
uint8_t _rsv0[0x1c]; // 0x4-0x1f
uint32_t cefuse; // 0x20
-} __attribute__((packed));
+} __packed;
static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse =
(void *)0x44e00a00;
diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h
index 4f4e635..41fc3d3 100644
--- a/src/cpu/ti/am335x/gpio.h
+++ b/src/cpu/ti/am335x/gpio.h
@@ -16,6 +16,7 @@
#define __CPU_TI_AM335X_GPIO_H__
#include <stdint.h>
+#include <compiler.h>
enum {
AM335X_GPIO_BITS_PER_BANK = 32
@@ -53,7 +54,7 @@ struct am335x_gpio_regs {
uint8_t _rsv4[0x38]; // 0x158-0x18f
uint32_t cleardataout; // 0x190
uint32_t setdataout; // 0x194
-} __attribute__((packed));
+} __packed;
static struct am335x_gpio_regs * const am335x_gpio_banks[] = {
(void *)0x44e07000, (void *)0x4804c000,
diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c
index 6837ef8..8802746 100644
--- a/src/cpu/ti/am335x/header.c
+++ b/src/cpu/ti/am335x/header.c
@@ -15,6 +15,7 @@
#include <config.h>
#include <stddef.h>
#include <stdint.h>
+#include <compiler.h>
#include <symbols.h>
#include "header.h"
@@ -26,7 +27,7 @@ struct config_headers {
// An inert instance of chsettings.
struct configuration_header_settings chsettings;
-} __attribute__((packed));
+} __packed;
struct omap_image_headers {
union {
diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h
index 43a6280..64d75c7 100644
--- a/src/cpu/ti/am335x/header.h
+++ b/src/cpu/ti/am335x/header.h
@@ -16,6 +16,7 @@
#define __CPU_TI_AM335X_HEADER_H
#include <stdint.h>
+#include <compiler.h>
struct configuration_header_toc_item {
// Offset from the start address of the TOC to the actual address of
@@ -30,7 +31,7 @@ struct configuration_header_toc_item {
// 12-character name of a section, including the zero (\0) terminator.
char filename[12];
-} __attribute__((packed));
+} __packed;
struct configuration_header_settings {
// Key used for section verification.
@@ -49,7 +50,7 @@ struct configuration_header_settings {
// Flags. It's not clear what this is used for.
uint32_t flags;
-} __attribute__((packed));
+} __packed;
struct gp_device_header {
// Size of the image.
@@ -57,6 +58,6 @@ struct gp_device_header {
// Address to store the image/code entry point.
uint32_t destination;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h
index 07c7cc8..7a65076 100644
--- a/src/cpu/ti/am335x/uart.h
+++ b/src/cpu/ti/am335x/uart.h
@@ -15,6 +15,8 @@
#ifndef AM335X_UART_H
#define AM335X_UART_H
+#include <compiler.h>
+
#define AM335X_UART0_BASE 0x44e09000
#define AM335X_UART1_BASE 0x48020000
#define AM335X_UART2_BASE 0x48024000
@@ -168,6 +170,6 @@ struct am335x_uart {
uint8_t rsvd_0x82[2];
uint16_t txdma; /* TX DMA threshold */
-} __attribute__((packed));
+} __packed;
#endif /* AM335X_UART_H */
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index b9084c7..48a1f20 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -103,14 +103,14 @@ struct sipi_params {
uint32_t msr_count;
uint32_t c_handler;
atomic_t ap_count;
-} __attribute__((packed));
+} __packed;
/* This also needs to match the assembly code for saved MSR encoding. */
struct saved_msr {
uint32_t index;
uint32_t lo;
uint32_t hi;
-} __attribute__((packed));
+} __packed;
/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 9be415d..e7fa411 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -2,10 +2,10 @@
2005.12 yhlu add ramstage cross the vga font buffer handling
*/
-#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/pae.h>
#include <string.h>
+#include <compiler.h>
static void paging_off(void)
{
@@ -48,11 +48,11 @@ void *map_2M_page(unsigned long page)
struct pde {
uint32_t addr_lo;
uint32_t addr_hi;
- } __attribute__ ((packed));
+ } __packed;
struct pg_table {
struct pde pd[2048];
struct pde pdp[512];
- } __attribute__ ((packed));
+ } __packed;
static struct pg_table pgtbl[CONFIG_MAX_CPUS] __attribute__ ((aligned(4096)));
static unsigned long mapped_window[CONFIG_MAX_CPUS];
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 853923d..b82bf8e 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -37,7 +37,7 @@ struct smm_stub_params {
u32 c_handler;
u32 c_handler_arg;
struct smm_runtime runtime;
-} __attribute__ ((packed));
+} __packed;
/*
* The stub is the entry point that sets up protected mode and stacks for each
@@ -60,7 +60,7 @@ extern unsigned char _binary_smm_start[];
struct smm_entry_ins {
char jmp_rel;
uint16_t rel16;
-} __attribute__ ((packed));
+} __packed;
/*
* Place the entry instructions for num entries beginning at entry_start with
diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c
index a1961bb..57c067b 100644
--- a/src/device/oprom/yabel/device.c
+++ b/src/device/oprom/yabel/device.c
@@ -56,7 +56,7 @@ typedef struct {
u8 cfg_space_offset;
u64 address;
u64 size;
-} __attribute__ ((__packed__)) assigned_address_t;
+} __packed assigned_address_t;
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
/* coreboot version */
diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h
index 72a4d53..471079f 100644
--- a/src/device/oprom/yabel/device.h
+++ b/src/device/oprom/yabel/device.h
@@ -62,7 +62,7 @@ typedef struct {
u16 bev; // Bootstrap Entry Vector
u16 reserved_2;
u16 sriv; // Static Resource Information Vector
-} __attribute__ ((__packed__)) exp_header_struct_t;
+} __packed exp_header_struct_t;
// a PCI Data Struct as defined in PCI 2.3 Spec Chapter 6.3.1.2
typedef struct {
@@ -78,7 +78,7 @@ typedef struct {
u8 code_type;
u8 indicator;
u16 reserved_2;
-} __attribute__ ((__packed__)) pci_data_struct_t;
+} __packed pci_data_struct_t;
typedef struct {
u8 bus;
@@ -116,7 +116,7 @@ typedef struct {
u64 address;
u64 address_offset;
u64 size;
-} __attribute__ ((__packed__)) translate_address_t;
+} __packed translate_address_t;
// array to store address translations for this
// device. Needed for faster address translation, so
diff --git a/src/device/oprom/yabel/pmm.h b/src/device/oprom/yabel/pmm.h
index c3abee3..2ecc36e 100644
--- a/src/device/oprom/yabel/pmm.h
+++ b/src/device/oprom/yabel/pmm.h
@@ -54,7 +54,7 @@ typedef struct {
* see interrupt.c) and the INT Handler will do the actual PMM work.
*/
u8 code[3];
-} __attribute__ ((__packed__)) pmm_information_t;
+} __packed pmm_information_t;
/* This function is used to setup the PMM struct in virtual memory
* at a certain offset */
diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c
index 9d717d8..a78ac71 100644
--- a/src/drivers/elog/boot_count.c
+++ b/src/drivers/elog/boot_count.c
@@ -43,7 +43,7 @@ struct boot_count {
u16 signature;
u32 count;
u16 checksum;
-} __attribute__ ((packed));
+} __packed;
/* Read and validate boot count structure from CMOS */
static int boot_count_cmos_read(struct boot_count *bc)
diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h
index d4fae4f..fd75cfe 100644
--- a/src/drivers/elog/elog_internal.h
+++ b/src/drivers/elog/elog_internal.h
@@ -22,7 +22,7 @@ struct elog_header {
u8 version;
u8 header_size;
u8 reserved[2];
-} __attribute__ ((packed));
+} __packed;
/* ELOG related constants */
#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */
@@ -40,7 +40,7 @@ struct event_header {
u8 hour;
u8 minute;
u8 second;
-} __attribute__ ((packed));
+} __packed;
/* SMBIOS Type 15 related constants */
#define ELOG_HEADER_TYPE_OEM 0x88
@@ -64,6 +64,6 @@ typedef enum elog_event_buffer_state {
struct elog_area {
struct elog_header header;
u8 data[0];
-} __attribute__((packed));
+} __packed;
#endif /* ELOG_INTERNAL_H_ */
diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c
index f125d23..8483e83 100644
--- a/src/drivers/elog/gsmi.c
+++ b/src/drivers/elog/gsmi.c
@@ -33,17 +33,17 @@ struct gsmi_set_eventlog_param {
u32 data_ptr;
u32 data_len;
u32 type;
-} __attribute__ ((packed));
+} __packed;
struct gsmi_set_eventlog_type1 {
u16 type;
u32 instance;
-} __attribute__ ((packed));
+} __packed;
struct gsmi_clear_eventlog_param {
u32 percentage;
u32 data_type;
-} __attribute__ ((packed));
+} __packed;
/* Param is usually EBX, ret in EAX */
u32 gsmi_exec(u8 command, u32 *param)
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index 625679d..c2de217 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -67,26 +67,26 @@ struct tpm_input_header {
uint16_t tag;
uint32_t length;
uint32_t ordinal;
-} __attribute__ ((packed));
+} __packed;
struct tpm_output_header {
uint16_t tag;
uint32_t length;
uint32_t return_code;
-} __attribute__ ((packed));
+} __packed;
struct timeout_t {
uint32_t a;
uint32_t b;
uint32_t c;
uint32_t d;
-} __attribute__ ((packed));
+} __packed;
struct duration_t {
uint32_t tpm_short;
uint32_t tpm_medium;
uint32_t tpm_long;
-} __attribute__ ((packed));
+} __packed;
typedef union {
struct timeout_t timeout;
@@ -97,12 +97,12 @@ struct tpm_getcap_params_in {
uint32_t cap;
uint32_t subcap_size;
uint32_t subcap;
-} __attribute__ ((packed));
+} __packed;
struct tpm_getcap_params_out {
uint32_t cap_size;
cap_t cap;
-} __attribute__ ((packed));
+} __packed;
typedef union {
struct tpm_input_header in;
@@ -117,7 +117,7 @@ typedef union {
struct tpm_cmd_t {
tpm_cmd_header header;
tpm_cmd_params params;
-} __attribute__ ((packed));
+} __packed;
/* ---------- Interface for TPM vendor ------------ */
diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h
index bbdd4de..badd254 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.h
+++ b/src/drivers/intel/fsp1_0/fsp_util.h
@@ -16,6 +16,7 @@
#ifndef FSP_UTIL_H
#define FSP_UTIL_H
+#include <compiler.h>
#include <chipset_fsp_util.h>
#include "fsp_values.h"
@@ -71,7 +72,7 @@ struct mrc_data_container {
u32 mrc_checksum; // IP style checksum
u32 reserved; // For header alignment
u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
+} __packed;
struct mrc_data_container *find_current_mrc_cache(void);
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 6e490d3..bdd981a 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -191,7 +191,7 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
struct fsp_runtime {
uint32_t fih;
uint32_t hob_list;
-} __attribute__((packed));
+} __packed;
void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h
index 8797932..6126380 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/gma.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/gma.h
@@ -18,6 +18,7 @@
#define _GMA_H_
#include <types.h>
+#include <compiler.h>
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
@@ -35,7 +36,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -72,7 +73,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -80,7 +81,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -99,7 +100,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -111,7 +112,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -120,7 +121,7 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
@@ -129,7 +130,7 @@ typedef struct {
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
@@ -146,7 +147,7 @@ typedef struct {
u8 codetype;
u8 indicator;
u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
+} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
@@ -170,7 +171,7 @@ typedef struct {
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
+} __packed optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c
index f4ba402..6dcfe69 100644
--- a/src/drivers/intel/fsp2_0/graphics.c
+++ b/src/drivers/intel/fsp2_0/graphics.c
@@ -37,7 +37,7 @@ struct hob_graphics_info {
uint32_t blue_mask;
uint32_t reserved_mask;
uint32_t pixels_per_scanline;
-} __attribute__((packed));
+} __packed;
struct pixel {
uint8_t pos;
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index c9d5b8e..e6f0a86 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -18,13 +18,14 @@
#include <inttypes.h>
#include <lib.h>
#include <string.h>
+#include <compiler.h>
#define HOB_HEADER_LEN 8
struct hob_header {
uint16_t type;
uint16_t length;
-} __attribute__((packed));
+} __packed;
struct hob_resource {
uint8_t owner_guid[16];
@@ -32,7 +33,7 @@ struct hob_resource {
uint32_t attribute_type;
uint64_t addr;
uint64_t length;
-} __attribute__((packed));
+} __packed;
enum resource_type {
EFI_RESOURCE_SYSTEM_MEMORY = 0,
diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch
index fc95f63..5365291 100644
--- a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch
+++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch
@@ -142,7 +142,7 @@ identifier s;
struct s {
...
}
-+ __attribute__((packed))
++ __packed
;
/*
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 004d91b..b5a75a4 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -12,6 +12,8 @@
#ifndef _FSP2_0_UPD_H_
#define _FSP2_0_UPD_H_
+#include <compiler.h>
+
struct FSP_UPD_HEADER {
///
/// UPD Region Signature. This signature will be
@@ -26,7 +28,7 @@ struct FSP_UPD_HEADER {
///
uint8_t Revision;
uint8_t Reserved[23];
-} __attribute__((packed));
+} __packed;
struct FSPM_ARCH_UPD {
///
@@ -59,6 +61,6 @@ struct FSPM_ARCH_UPD {
///
uint32_t BootMode;
uint8_t Reserved1[8];
-} __attribute__((packed));
+} __packed;
#endif /* _FSP2_0_UPD_H_ */
diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h
index 7b5edd3..ac0c651 100644
--- a/src/drivers/intel/gma/intel_bios.h
+++ b/src/drivers/intel/gma/intel_bios.h
@@ -28,6 +28,8 @@
#ifndef _I830_BIOS_H_
#define _I830_BIOS_H_
+#include <compiler.h>
+
struct vbt_header {
u8 signature[20]; /**< Always starts with 'VBT$' */
u16 version; /**< decimal */
@@ -37,7 +39,7 @@ struct vbt_header {
u8 reserved0;
u32 bdb_offset; /**< from beginning of VBT */
u32 aim_offset[4]; /**< from beginning of VBT */
-} __attribute__((packed));
+} __packed;
struct bdb_header {
u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
@@ -63,7 +65,7 @@ struct vbios_data {
u8 rsvd4; /* popup memory size */
u8 resize_pci_bios;
u8 rsvd5; /* is crt already on ddc2 */
-} __attribute__((packed));
+} __packed;
/*
* There are several types of BIOS data blocks (BDBs), each block has
@@ -140,7 +142,7 @@ struct bdb_general_features {
u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
u8 rsvd11:3; /* finish byte */
-} __attribute__((packed));
+} __packed;
/* pre-915 */
#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
@@ -223,7 +225,7 @@ struct old_child_dev_config {
u8 dvo2_wiring;
u16 extended_type;
u8 dvo_function;
-} __attribute__((packed));
+} __packed;
/* This one contains field offsets that are known to be common for all BDB
* versions. Notice that the meaning of the contents contents may still change,
@@ -236,7 +238,7 @@ struct common_child_dev_config {
u8 not_common2[2];
u8 ddc_pin;
u16 edid_ptr;
-} __attribute__((packed));
+} __packed;
/* This field changes depending on the BDB version, so the most reliable way to
* read it is by checking the BDB version and reading the raw pointer. */
@@ -277,7 +279,7 @@ struct bdb_general_definitions {
* sizeof(child_device_config);
*/
union child_device_config devices[0];
-} __attribute__((packed));
+} __packed;
struct bdb_lvds_options {
u8 panel_type;
@@ -291,7 +293,7 @@ struct bdb_lvds_options {
u8 lvds_edid:1;
u8 rsvd2:1;
u8 rsvd4;
-} __attribute__((packed));
+} __packed;
/* LFP pointer table contains entries to the struct below */
struct bdb_lvds_lfp_data_ptr {
@@ -301,12 +303,12 @@ struct bdb_lvds_lfp_data_ptr {
u8 dvo_table_size;
u16 panel_pnp_id_offset;
u8 pnp_table_size;
-} __attribute__((packed));
+} __packed;
struct bdb_lvds_lfp_data_ptrs {
u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
struct bdb_lvds_lfp_data_ptr ptr[16];
-} __attribute__((packed));
+} __packed;
/* LFP data has 3 blocks per entry */
struct lvds_fp_timing {
@@ -323,7 +325,7 @@ struct lvds_fp_timing {
u32 pfit_reg;
u32 pfit_reg_val;
u16 terminator;
-} __attribute__((packed));
+} __packed;
struct lvds_dvo_timing {
u16 clock; /**< In 10khz */
@@ -351,7 +353,7 @@ struct lvds_dvo_timing {
u8 vsync_positive:1;
u8 hsync_positive:1;
u8 rsvd2:1;
-} __attribute__((packed));
+} __packed;
struct lvds_pnp_id {
u16 mfg_name;
@@ -359,17 +361,17 @@ struct lvds_pnp_id {
u32 serial;
u8 mfg_week;
u8 mfg_year;
-} __attribute__((packed));
+} __packed;
struct bdb_lvds_lfp_data_entry {
struct lvds_fp_timing fp_timing;
struct lvds_dvo_timing dvo_timing;
struct lvds_pnp_id pnp_id;
-} __attribute__((packed));
+} __packed;
struct bdb_lvds_lfp_data {
struct bdb_lvds_lfp_data_entry data[16];
-} __attribute__((packed));
+} __packed;
struct aimdb_header {
char signature[16];
@@ -377,12 +379,12 @@ struct aimdb_header {
u16 aimdb_version;
u16 aimdb_header_size;
u16 aimdb_size;
-} __attribute__((packed));
+} __packed;
struct aimdb_block {
u8 aimdb_id;
u16 aimdb_size;
-} __attribute__((packed));
+} __packed;
struct vch_panel_data {
u16 fp_timing_offset;
@@ -393,12 +395,12 @@ struct vch_panel_data {
u8 text_fitting_size;
u16 graphics_fitting_offset;
u8 graphics_fitting_size;
-} __attribute__((packed));
+} __packed;
struct vch_bdb_22 {
struct aimdb_block aimdb_block;
struct vch_panel_data panels[16];
-} __attribute__((packed));
+} __packed;
struct bdb_sdvo_lvds_options {
u8 panel_backlight;
@@ -414,7 +416,7 @@ struct bdb_sdvo_lvds_options {
u8 panel_misc_bits_2;
u8 panel_misc_bits_3;
u8 panel_misc_bits_4;
-} __attribute__((packed));
+} __packed;
#define BDB_DRIVER_FEATURE_NO_LVDS 0
@@ -460,7 +462,7 @@ struct bdb_driver_features {
u8 hdmi_termination;
u8 custom_vbt_version;
-} __attribute__((packed));
+} __packed;
#define EDP_18BPP 0
#define EDP_24BPP 1
@@ -485,14 +487,14 @@ struct edp_power_seq {
u16 t9;
u16 t10;
u16 t11_t12;
-} __attribute__ ((packed));
+} __packed;
struct edp_link_params {
u8 rate:4;
u8 lanes:4;
u8 preemphasis:4;
u8 vswing:4;
-} __attribute__ ((packed));
+} __packed;
struct bdb_edp {
struct edp_power_seq power_seqs[16];
@@ -503,7 +505,7 @@ struct bdb_edp {
/* ith bit indicates enabled/disabled for (i+1)th panel */
u16 edp_s3d_feature;
u16 edp_t3_optimization;
-} __attribute__ ((packed));
+} __packed;
/*
* Driver<->VBIOS interaction occurs through scratch bits in
@@ -728,7 +730,7 @@ struct bdb_mipi {
u32 hl_switch_cnt;
u32 lp_byte_clk;
u32 clk_lane_switch_cnt;
-} __attribute__((packed));
+} __packed;
/* Intel Video BIOS (Option ROM) */
typedef struct {
@@ -737,7 +739,7 @@ typedef struct {
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
@@ -754,7 +756,7 @@ typedef struct {
u8 codetype;
u8 indicator;
u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
+} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
@@ -778,7 +780,7 @@ typedef struct {
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
+} __packed optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index 5661bf4..42732a9 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -34,7 +34,7 @@ static int smbios_write_wifi(struct device *dev, int *handle,
u16 handle;
u8 str;
char eos[2];
- } __attribute__((packed));
+ } __packed;
struct smbios_type_intel_wifi *t =
(struct smbios_type_intel_wifi *)*current;
diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h
index 886f3dd..d790a14 100644
--- a/src/drivers/siemens/nc_fpga/nc_fpga.h
+++ b/src/drivers/siemens/nc_fpga/nc_fpga.h
@@ -16,6 +16,8 @@
#ifndef _SIEMENS_NC_FPGA_H_
#define _SIEMENS_NC_FPGA_H_
+#include <compiler.h>
+
#define NC_MAGIC_OFFSET 0x020
#define NC_FPGA_MAGIC 0x4E433746
#define NC_CAP1_OFFSET 0x080
@@ -59,6 +61,6 @@ typedef struct {
uint16_t hystthreshold;
uint16_t res9[4];
uint32_t fanmon;
-} __attribute__ ((packed)) fan_ctrl_t;
+} __packed fan_ctrl_t;
#endif /* _SIEMENS_NC_FPGA_H_ */
diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h
index 25c08a0..e86286a 100644
--- a/src/drivers/usb/ehci.h
+++ b/src/drivers/usb/ehci.h
@@ -52,7 +52,7 @@ struct ehci_caps {
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
u8 portroute[8]; /* nibbles for routing - offset 0xC */
-} __attribute__ ((packed));
+} __packed;
/* Section 2.3 Host Controller Operational Registers */
@@ -148,7 +148,7 @@ struct ehci_regs {
#define PORT_CSC (1<<1) /* connect status change */
#define PORT_CONNECT (1<<0) /* device connected */
#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
-} __attribute__ ((packed));
+} __packed;
#define USBMODE 0x68 /* USB Device mode */
#define USBMODE_SDIS (1<<3) /* Stream disable */
@@ -192,7 +192,7 @@ struct ehci_dbg_port {
u32 data47;
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
-} __attribute__ ((packed));
+} __packed;
#define USB_DEBUG_DEVNUM 127
diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h
index 4509287..67ce8f0 100644
--- a/src/drivers/usb/usb_ch9.h
+++ b/src/drivers/usb/usb_ch9.h
@@ -111,7 +111,7 @@ struct usb_ctrlrequest {
u16 wValue;
u16 wIndex;
u16 wLength;
-} __attribute__ ((packed));
+} __packed;
struct usb_debug_descriptor {
u8 bLength;
diff --git a/src/include/compiler.h b/src/include/compiler.h
new file mode 100644
index 0000000..293d659
--- /dev/null
+++ b/src/include/compiler.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#define __packed __attribute__((packed))
+#define __aligned(x) __attribute__((aligned(x)))
+#define __always_unused __attribute((unused))
+
+#endif
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
index bf58a36..9e3a005 100644
--- a/src/include/console/spi.h
+++ b/src/include/console/spi.h
@@ -18,6 +18,7 @@
#include <rules.h>
#include <stdint.h>
+#include <compiler.h>
void spiconsole_init(void);
void spiconsole_tx_byte(unsigned char c);
@@ -56,13 +57,11 @@ struct em100_msg_header {
uint32_t msg_signature;
uint8_t msg_type;
uint8_t msg_length;
-} __attribute__ ((packed));
+} __packed;
struct em100_msg {
struct em100_msg_header header;
char data[MAX_MSG_LENGTH];
-} __attribute__ ((packed));
-
-
+} __packed;
#endif /* CONSOLE_SPI_H */
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 2b13f8c..3e5b010 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -22,6 +22,7 @@
#include <arch/cpu.h>
#include <types.h>
+#include <compiler.h>
#define SMM_DEFAULT_BASE 0x30000
#define SMM_DEFAULT_SIZE 0x10000
@@ -124,7 +125,7 @@ typedef struct {
u64 rdx;
u64 rcx;
u64 rax;
-} __attribute__((packed)) amd64_smm_state_save_area_t;
+} __packed amd64_smm_state_save_area_t;
/* Intel Core 2 (EM64T) SMM State-Save Area
@@ -202,7 +203,7 @@ typedef struct {
u64 cr3;
u64 cr0;
-} __attribute__((packed)) em64t_smm_state_save_area_t;
+} __packed em64t_smm_state_save_area_t;
/* Intel Revision 30100 SMM State-Save Area
@@ -289,7 +290,7 @@ typedef struct {
u64 cr3;
u64 cr0;
-} __attribute__((packed)) em64t100_smm_state_save_area_t;
+} __packed em64t100_smm_state_save_area_t;
/* Intel Revision 30101 SMM State-Save Area
* The following processor architectures use this:
@@ -388,7 +389,7 @@ typedef struct {
u64 cr3;
u64 cr0;
-} __attribute__((packed)) em64t101_smm_state_save_area_t;
+} __packed em64t101_smm_state_save_area_t;
/* Legacy x86 SMM State-Save Area
@@ -428,7 +429,7 @@ typedef struct {
u32 eflags;
u32 cr3;
u32 cr0;
-} __attribute__((packed)) legacy_smm_state_save_area_t;
+} __packed legacy_smm_state_save_area_t;
typedef enum {
AMD64,
@@ -498,7 +499,7 @@ struct smm_runtime {
* contiguous like the 1:1 mapping it is up to the caller of the stub
* loader to adjust this mapping. */
u8 apic_id_to_cpu[CONFIG_MAX_CPUS];
-} __attribute__ ((packed));
+} __packed;
struct smm_module_params {
void *arg;
diff --git a/src/include/elog.h b/src/include/elog.h
index b94a281..ae320af 100644
--- a/src/include/elog.h
+++ b/src/include/elog.h
@@ -16,6 +16,8 @@
#ifndef ELOG_H_
#define ELOG_H_
+#include <compiler.h>
+
/* SMI command code for GSMI event logging */
#define ELOG_GSMI_APM_CNT 0xEF
@@ -112,7 +114,7 @@
struct elog_event_data_wake {
u8 source;
u32 instance;
-} __attribute__ ((packed));
+} __packed;
/* Chrome OS related events */
#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
@@ -130,7 +132,7 @@ struct elog_event_data_me_extended {
u8 progress_code;
u8 current_pmevent;
u8 current_state;
-} __attribute__ ((packed));
+} __packed;
/* Last post code from previous boot */
#define ELOG_TYPE_LAST_POST_CODE 0xa3
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 4613628..7e84fb5 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -16,6 +16,8 @@
#ifndef _MEMORY_INFO_H_
#define _MEMORY_INFO_H_
+#include <compiler.h>
+
/*
* If this table is filled and put in CBMEM,
* then these info in CBMEM will be used to generate smbios type 17 table
@@ -35,12 +37,12 @@ struct dimm_info {
uint16_t mod_id;
uint8_t mod_type;
uint8_t bus_width;
-} __attribute__((packed));
+} __packed;
struct memory_info {
uint8_t dimm_cnt;
/* Maximum num of dimm is 8 */
struct dimm_info dimm[8];
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 0400262..54eab05 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -18,6 +18,7 @@
#define SMBIOS_H
#include <types.h>
+#include <compiler.h>
unsigned long smbios_write_tables(unsigned long start);
int smbios_add_string(char *start, const char *str);
@@ -229,7 +230,7 @@ struct smbios_entry {
u32 struct_table_address;
u16 struct_count;
u8 smbios_bcd_revision;
-} __attribute__((packed));
+} __packed;
struct smbios_type0 {
u8 type;
@@ -248,7 +249,7 @@ struct smbios_type0 {
u8 ec_major_release;
u8 ec_minor_release;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type1 {
u8 type;
@@ -263,7 +264,7 @@ struct smbios_type1 {
u8 sku;
u8 family;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type2 {
u8 type;
@@ -274,7 +275,7 @@ struct smbios_type2 {
u8 version;
u8 serial_number;
char eos[2];
-} __attribute__((packed));
+} __packed;
enum
{
@@ -301,7 +302,7 @@ struct smbios_type3 {
u8 element_count;
u8 element_record_length;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type4 {
u8 type;
@@ -331,7 +332,7 @@ struct smbios_type4 {
u16 processor_characteristics;
u16 processor_family2;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type11 {
u8 type;
@@ -339,7 +340,7 @@ struct smbios_type11 {
u16 handle;
u8 count;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type15 {
u8 type;
@@ -356,7 +357,7 @@ struct smbios_type15 {
u8 log_type_descriptors;
u8 log_type_descriptor_length;
char eos[2];
-} __attribute__((packed));
+} __packed;
enum {
SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0,
@@ -383,7 +384,7 @@ struct smbios_type16 {
u16 number_of_memory_devices;
u64 extended_maximum_capacity;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type17 {
u8 type;
@@ -412,7 +413,7 @@ struct smbios_type17 {
u16 maximum_voltage;
u16 configured_voltage;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type32 {
u8 type;
@@ -421,7 +422,7 @@ struct smbios_type32 {
u8 reserved[6];
u8 boot_status;
u8 eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type38 {
u8 type;
@@ -434,7 +435,7 @@ struct smbios_type38 {
u64 base_address;
u8 base_address_modifier;
u8 irq;
-} __attribute__((packed));
+} __packed;
typedef enum {
SMBIOS_DEVICE_TYPE_OTHER = 0x01,
@@ -462,14 +463,14 @@ struct smbios_type41 {
u8 function_number: 3;
u8 device_number: 5;
char eos[2];
-} __attribute__((packed));
+} __packed;
struct smbios_type127 {
u8 type;
u8 length;
u16 handle;
u8 eos[2];
-} __attribute__((packed));
+} __packed;
void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t);
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 009dabd..2f5059d 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -13,6 +13,7 @@
#ifndef VBE_H
#define VBE_H
+#include <compiler.h>
#include <boot/coreboot_tables.h>
// these structs are for input from and output to OF
typedef struct {
@@ -23,7 +24,7 @@ typedef struct {
u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
-} __attribute__ ((__packed__)) screen_info_t;
+} __packed screen_info_t;
typedef struct {
u8 signature[4];
@@ -31,7 +32,7 @@ typedef struct {
u8 monitor_number;
u16 max_screen_width;
u8 color_depth;
-} __attribute__ ((__packed__)) screen_info_input_t;
+} __packed screen_info_input_t;
// these structs only store a subset of the VBE defined fields
// only those needed.
@@ -78,7 +79,7 @@ typedef struct {
u32 offscreen_mem_offset;
u16 offscreen_mem_size;
u8 reserved[206];
-} __attribute__ ((__packed__)) vesa_mode_info_t;
+} __packed vesa_mode_info_t;
typedef struct {
u16 video_mode;
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index f399f64..68547a3 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -17,6 +17,7 @@
#include <console/cbmem_console.h>
#include <console/uart.h>
#include <cbmem.h>
+#include <compiler.h>
#include <arch/early_variables.h>
#include <symbols.h>
#include <string.h>
@@ -31,7 +32,7 @@ struct cbmem_console {
u32 buffer_size;
u32 buffer_cursor;
u8 buffer_body[0];
-} __attribute__ ((__packed__));
+} __packed;
static struct cbmem_console *cbmem_console_p CAR_GLOBAL;
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 2fc6fac..6280ae5 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -15,6 +15,7 @@
#include <assert.h>
#include <cbmem.h>
+#include <compiler.h>
#include <console/console.h>
#include <imd.h>
#include <stdlib.h>
@@ -32,7 +33,7 @@ struct imd_root_pointer {
uint32_t magic;
/* Relative to upper limit/offset. */
int32_t root_offset;
-} __attribute__((packed));
+} __packed;
struct imd_entry {
uint32_t magic;
@@ -40,7 +41,7 @@ struct imd_entry {
int32_t start_offset;
uint32_t size;
uint32_t id;
-} __attribute__((packed));
+} __packed;
struct imd_root {
uint32_t max_entries;
@@ -50,7 +51,7 @@ struct imd_root {
/* Used for fixing the size of an imd. Relative to the root. */
int32_t max_offset;
struct imd_entry entries[0];
-} __attribute__((packed));
+} __packed;
#define IMD_FLAG_LOCKED 1
diff --git a/src/lib/tpm2_tlcl_structures.h b/src/lib/tpm2_tlcl_structures.h
index 36a3e8b..58e447c 100644
--- a/src/lib/tpm2_tlcl_structures.h
+++ b/src/lib/tpm2_tlcl_structures.h
@@ -56,7 +56,7 @@ struct tpm_header {
uint16_t tpm_tag;
uint32_t tpm_size;
TPM_CC tpm_code;
-} __attribute__((packed));
+} __packed;
/* TPM command codes. */
#define TPM2_Clear ((TPM_CC)0x00000126)
@@ -290,7 +290,7 @@ struct tpm2_session_header {
union {
struct tpm2_session_attrs session_attr_bits;
uint8_t session_attrs;
- } __attribute__((packed));
+ } __packed;
uint16_t auth_size;
uint8_t *auth;
};
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 9f6a55c..9e33feb 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -185,7 +185,7 @@ struct BiosLinkerLoaderEntry {
/* padding */
char pad[124];
};
-} __attribute__((packed));
+} __packed;
typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
enum {
diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h
index 533607c..a690466 100644
--- a/src/mainboard/siemens/mc_tcu3/ptn3460.h
+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h
@@ -17,6 +17,7 @@
#define PTN3460_H_
#include <delay.h>
+#include <compiler.h>
#include "lcd_panel.h"
#define PTN_SLAVE_ADR 0x20
@@ -56,13 +57,13 @@ struct ptn_3460_config{
u8 t2_delay; /* Panel T2 delay */
u8 t4_timing; /* Panel T4 timing value */
u8 t5_delay; /* Panel T5 delay */
-}__attribute__((packed));
+} __packed;
struct ptn_3460_flash{
u8 cmd; /* Flash command (erase or erase and flash) */
u16 magic; /* Magic number needed by the flash algorithm */
u8 trigger; /* Trigger for starting flash operation */
-}__attribute__((packed));
+} __packed;
int ptn3460_init(char *hwi_block);
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
index ad6687e..92805d3 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
@@ -41,7 +41,7 @@ typedef struct {
u32 pcba;
u8 mpen;
u8 reserv[247];
-} __attribute__((packed)) global_vars_t;
+} __packed global_vars_t;
static void acpi_write_gvars(global_vars_t *gvars)
{
diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c
index ec4d07a..0705b47 100644
--- a/src/mainboard/via/epia-m700/wakeup.c
+++ b/src/mainboard/via/epia-m700/wakeup.c
@@ -52,9 +52,9 @@ static unsigned long long real_mode_gdt_entries[3] = {
struct Xgt_desc_struct {
unsigned short size;
- unsigned long address __attribute__ ((packed));
+ unsigned long address __packed;
unsigned short pad;
-} __attribute__ ((packed));
+} __packed;
static struct Xgt_desc_struct real_mode_gdt = {
sizeof(real_mode_gdt_entries) - 1,
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index c0bfc5a..5d8abf9 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -16,6 +16,8 @@
#ifndef AMDFAM10_H
+#include <compiler.h>
+
#define AMDFAM10_H
/* Definitions of various FAM10 registers */
/* Function 0 */
@@ -994,14 +996,14 @@ struct link_pair_t {
u8 nodeid;
u8 linkn;
u8 rsv;
-} __attribute__((packed));
+} __packed;
struct nodes_info_t {
u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8
u32 groups_in_plane; // could be 1, 2, 3, 4, 5
u32 planes; // could be 1, 2
u32 up_planes; // down planes will be [up_planes, planes)
-} __attribute__((packed));
+} __packed;
struct ht_link_config {
uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default)
@@ -1037,7 +1039,7 @@ struct sys_info {
struct MCTStatStruc MCTstat;
struct DCTStatStruc DCTstatA[NODE_NUMS];
-} __attribute__((packed));
+} __packed;
#ifdef __PRE_RAM__
extern struct sys_info sysinfo_car;
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index af4658d..680b30c 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -456,6 +456,7 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
+#include <compiler.h>
#include "raminit.h"
//struct definitions
@@ -465,7 +466,7 @@ struct dimm_size {
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
-} __attribute__((packed));
+} __packed;
struct mem_info { // pernode
uint32_t dimm_mask;
@@ -483,7 +484,7 @@ struct mem_info { // pernode
uint8_t is_64MuxMode;
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t rsv[2];
-} __attribute__((packed));
+} __packed;
struct link_pair_st {
device_t udev;
@@ -493,7 +494,7 @@ struct link_pair_st {
uint32_t pos;
uint32_t offs;
-} __attribute__((packed));
+} __packed;
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
@@ -516,7 +517,7 @@ struct sys_info {
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
-} __attribute__((packed));
+} __packed;
#ifdef __PRE_RAM__
#include <arch/early_variables.h>
diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h
index c413b5b..9358e13 100644
--- a/src/northbridge/amd/amdk8/pre_f.h
+++ b/src/northbridge/amd/amdk8/pre_f.h
@@ -236,6 +236,7 @@
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
+#include <compiler.h>
#include "raminit.h"
//struct definitions
@@ -247,7 +248,7 @@ struct link_pair_st {
uint32_t pos;
uint32_t offs;
-} __attribute__((packed));
+} __packed;
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
@@ -260,7 +261,7 @@ struct sys_info {
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
-} __attribute__((packed));
+} __packed;
#ifdef __PRE_RAM__
#include <arch/early_variables.h>
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index b580457..d568935 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -20,7 +20,7 @@
#ifndef MCT_D_H
#define MCT_D_H
-
+#include <compiler.h>
/*===========================================================================
CPU - K8/FAM10
@@ -264,7 +264,7 @@ struct MCTStatStruc {
of sub 4GB dram hole for HW remapping.*/
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
u32 SysLimit; /* LIMIT[39:8] (system address)*/
-} __attribute__((packed));
+} __packed;
/*=============================================================================
Global MCT Configuration Status Word (GStatus)
@@ -531,7 +531,7 @@ struct DCTStatStruc { /* A per Node structure*/
char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH+1];
uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED];
uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED];
-} __attribute__((packed));
+} __packed;
/*===============================================================================
Local Error Status Codes (DCTStatStruc.ErrCode)
@@ -697,7 +697,7 @@ struct amdmct_memory_info {
struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED];
uint16_t ecc_enabled;
uint16_t ecc_scrub_rate;
-} __attribute__((packed));
+} __packed;
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h
index 1fb6667..c874cd9 100644
--- a/src/northbridge/intel/common/mrc_cache.h
+++ b/src/northbridge/intel/common/mrc_cache.h
@@ -10,7 +10,7 @@ struct mrc_data_container {
u32 mrc_checksum; // IP style checksum
u32 reserved; // For header alignment
u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
+} __packed;
struct mrc_data_container *find_current_mrc_cache(void);
struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length);
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h
index 5693e0c..87f1f3c 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.h
+++ b/src/northbridge/intel/fsp_sandybridge/gma.h
@@ -26,7 +26,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -63,7 +63,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -71,7 +71,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -90,7 +90,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -102,7 +102,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -111,7 +111,7 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
@@ -120,7 +120,7 @@ typedef struct {
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
@@ -137,7 +137,7 @@ typedef struct {
u8 codetype;
u8 indicator;
u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
+} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
@@ -161,7 +161,7 @@ typedef struct {
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
+} __packed optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h
index 5adab57..820e432 100644
--- a/src/northbridge/intel/haswell/gma.h
+++ b/src/northbridge/intel/haswell/gma.h
@@ -26,7 +26,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -63,7 +63,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -71,7 +71,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -90,7 +90,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -102,7 +102,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -111,7 +111,7 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
@@ -120,7 +120,7 @@ typedef struct {
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
@@ -137,7 +137,7 @@ typedef struct {
u8 codetype;
u8 indicator;
u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
+} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
@@ -161,7 +161,7 @@ typedef struct {
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
+} __packed optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 6e587f8..df614a4 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -192,7 +192,7 @@ struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
#define PCI_DEVICE_ID_HSW_ULT 0x0a04
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index f92c0a6..319b9e7 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -56,12 +56,12 @@ struct usb2_port_setting {
uint8_t enable;
uint8_t over_current_pin;
uint8_t location;
-} __attribute__((packed));
+} __packed;
struct usb3_port_setting {
uint8_t enable;
uint8_t over_current_pin;
-} __attribute__((packed));
+} __packed;
struct pei_data
{
@@ -110,6 +110,6 @@ struct pei_data
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
uint8_t spd_data[4][256];
tx_byte_func tx_byte;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index 12da698..4136f77 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -51,7 +51,7 @@ typedef struct {
u32 function;
u32 retsts;
u32 rfu;
-} __attribute__((packed)) banner_id_t;
+} __packed banner_id_t;
#define MSH_OK 0x0000
#define MSH_OK_RESTART 0x0001
@@ -111,7 +111,7 @@ typedef struct {
u16 versionmajor;
u16 versionminor;
u32 smicombuffersize;
-} __attribute__((packed)) version_t;
+} __packed version_t;
typedef struct {
u16 header_id;
@@ -122,14 +122,14 @@ typedef struct {
u32 type;
u32 header_ext;
u8 name[0];
-} __attribute__((packed)) mbi_header_t;
+} __packed mbi_header_t;
typedef struct {
banner_id_t banner;
u64 handle;
u32 objnum;
mbi_header_t header;
-} __attribute__((packed)) obj_header_t;
+} __packed obj_header_t;
typedef struct {
banner_id_t banner;
@@ -139,7 +139,7 @@ typedef struct {
u32 numbytes;
u32 buflen;
u32 buffer;
-} __attribute__((packed)) get_object_t;
+} __packed get_object_t;
static void mbi_call(u8 subf, banner_id_t *banner_id)
{
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 6c7ae96..77f270b 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -61,7 +61,7 @@ struct sys_info {
u8 banksize[2 * 2 * DIMM_SOCKETS];
const u8 *spd_addresses;
-} __attribute__ ((packed));
+} __packed;
void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses);
diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h
index 92d6fbe..8a215b4 100644
--- a/src/northbridge/intel/nehalem/gma.h
+++ b/src/northbridge/intel/nehalem/gma.h
@@ -27,7 +27,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -64,7 +64,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -72,7 +72,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -91,7 +91,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -103,7 +103,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -112,6 +112,6 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 69e7108..3819ba4 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1906,7 +1906,7 @@ static void send_heci_uma_message(struct raminfo *info)
u8 result;
u8 field2;
u8 unk3[0x48 - 4 - 1];
- } __attribute__ ((packed)) reply;
+ } __packed reply;
struct uma_message {
u8 group_id;
u8 cmd;
@@ -1916,7 +1916,7 @@ static void send_heci_uma_message(struct raminfo *info)
u64 heci_uma_addr;
u32 memory_reserved_for_heci_mb;
u16 c3;
- } __attribute__ ((packed)) msg = {
+ } __packed msg = {
0, MKHI_SET_UMA, 0, 0,
0x82,
info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0};
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 534b42e..c1490f1 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -16,6 +16,8 @@
#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H
#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H
+#include <compiler.h>
+
/* mailbox 0: header */
typedef struct {
u8 signature[16];
@@ -26,7 +28,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -63,7 +65,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -71,7 +73,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -90,7 +92,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -102,7 +104,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -111,7 +113,7 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
struct i915_gpu_controller_info;
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 136d310..00534ca 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -129,6 +129,6 @@ struct pei_data
* 2 Always enable double rate
*/
int ddr_refresh_rate_config;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index 4e684ec..4bc9de6 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -23,7 +23,7 @@ struct sys_info {
#define BOOT_PATH_NORMAL 0
#define BOOT_PATH_RESET 1
#define BOOT_PATH_RESUME 2
-} __attribute__ ((packed));
+} __packed;
void sdram_initialize(struct pei_data *pei_data);
void save_mrc_data(struct pei_data *pei_data);
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
index 3712fd7..e51e328 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
@@ -47,13 +47,13 @@ struct DIMM_INFO {
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
uint8_t ModulePartNum[20];
-} __attribute__((packed));
+} __packed;
struct CHANNEL_INFO {
uint8_t ChannelId;
uint8_t DimmCount;
struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
-} __attribute__((packed));
+} __packed;
struct FSP_SMBIOS_MEMORY_INFO {
uint8_t Revision;
@@ -69,7 +69,7 @@ struct FSP_SMBIOS_MEMORY_INFO {
uint8_t ErrorCorrectionType;
uint8_t ChannelCount;
struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
-} __attribute__((packed));
+} __packed;
/** Fsp M Configuration
@@ -574,7 +574,7 @@ struct FSP_M_CONFIG {
/** Offset 0x0136
**/
uint8_t ReservedFspmUpd[26];
-} __attribute__((packed));
+} __packed;
/** Fsp M Test Configuration
**/
@@ -587,7 +587,7 @@ struct FSP_M_TEST_CONFIG {
/** Offset 0x0154
**/
uint8_t ReservedFspmTestUpd[28];
-} __attribute__((packed));
+} __packed;
/** Fsp M Restricted Configuration
**/
@@ -600,7 +600,7 @@ struct FSP_M_RESTRICTED_CONFIG {
/** Offset 0x0174
**/
uint8_t ReservedFspmRestrictedUpd[138];
-} __attribute__((packed));
+} __packed;
/** Fsp M UPD Configuration
**/
@@ -629,6 +629,6 @@ struct FSPM_UPD {
/** Offset 0x01FE
**/
uint16_t UpdTerminator;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
index 25346be..ee1f39d 100644
--- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
+++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
@@ -1483,7 +1483,7 @@ struct FSP_S_CONFIG {
/** Offset 0x0328
**/
uint8_t ReservedFspsUpd[8];
-} __attribute__((packed));
+} __packed;
/** Fsp S Test Configuration
**/
@@ -1496,7 +1496,7 @@ struct FSP_S_TEST_CONFIG {
/** Offset 0x0334
**/
uint8_t ReservedFspsTestUpd[12];
-} __attribute__((packed));
+} __packed;
/** Fsp S Restricted Configuration
**/
@@ -1509,7 +1509,7 @@ struct FSP_S_RESTRICTED_CONFIG {
/** Offset 0x0344
**/
uint8_t ReservedFspsRestrictedUpd[12];
-} __attribute__((packed));
+} __packed;
/** Fsp S UPD Configuration
**/
@@ -1534,6 +1534,6 @@ struct FSPS_UPD {
/** Offset 0x0350
**/
uint16_t UpdTerminator;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index bff949e..afff43a 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -42,6 +42,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index d8eb50b..3cc0909 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -158,7 +158,7 @@ struct chipset_power_state {
uint32_t gen_pmcon2;
uint32_t gen_pmcon3;
uint32_t prev_sleep_state;
-} __attribute__((packed));
+} __packed;
int fill_power_state(struct chipset_power_state *ps);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index 5ac95e4..b4fe65e 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
#define _BAYTRAIL_DEVICE_NVS_H_
#include <stdint.h>
+#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
@@ -59,6 +60,6 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
#endif
diff --git a/src/soc/intel/baytrail/include/soc/efi_wrapper.h b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
index 3304d03..3425aae 100644
--- a/src/soc/intel/baytrail/include/soc/efi_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
@@ -29,6 +29,8 @@
#ifndef __EFI_WRAPPER_H__
#define __EFI_WRAPPER_H__
+#include <compiler.h>
+
#define EFI_WRAPPER_VER 2
/* Provide generic x86 calling conventions. */
@@ -46,7 +48,7 @@ struct efi_wrapper_params {
void ABI_X86 (*console_out)(unsigned char byte);
unsigned int tsc_ticks_per_microsecond;
-} __attribute__((packed));
+} __packed;
typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
#endif
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 79c19b4..7b30ced 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -17,6 +17,7 @@
#define _BAYTRAIL_GPIO_H_
#include <stdint.h>
+#include <compiler.h>
#include <arch/io.h>
#include <soc/iomap.h>
@@ -350,7 +351,7 @@ struct soc_gpio_map {
u32 smi : 1;
u32 is_gpio : 1;
u32 sci : 1;
-} __attribute__ ((packed));
+} __packed;
struct soc_gpio_config {
const struct soc_gpio_map *ncore;
diff --git a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
index 355dce0..d3547c2 100644
--- a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
@@ -28,6 +28,8 @@
#ifndef _MRC_WRAPPER_H_
#define _MRC_WRAPPER_H_
+#include <compiler.h>
+
#define MRC_PARAMS_VER 5
#define NUM_CHANNELS 2
@@ -76,7 +78,7 @@ struct mrc_mainboard_params {
int dram_odt_value;
int spd_addrs[NUM_CHANNELS];
void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */
-} __attribute__((packed));
+} __packed;
struct mrc_params {
/* Mainboard Inputs */
@@ -99,7 +101,7 @@ struct mrc_params {
void *txe_base_address;
int data_to_save_size;
void *data_to_save;
-} __attribute__((packed));
+} __packed;
/* Call into wrapper. */
typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *);
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cb4e9bf..8e6819d 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -17,6 +17,7 @@
#ifndef _BAYTRAIL_NVS_H_
#define _BAYTRAIL_NVS_H_
+#include <compiler.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
@@ -64,7 +65,7 @@ typedef struct {
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index c8d6a67..fc8bc97 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -250,6 +250,7 @@
# define SYS_RST (1 << 1)
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+#include <compiler.h>
/* Track power state from reset to log events. */
struct chipset_power_state {
@@ -262,7 +263,7 @@ struct chipset_power_state {
uint32_t prsts;
uint32_t gen_pmcon1;
uint32_t gen_pmcon2;
-} __attribute__((packed));
+} __packed;
/* Power Management Utility Functions. */
uint16_t get_pmbase(void);
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index ffe6198..71714fd 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <bootstate.h>
#include <delay.h>
+#include <compiler.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
@@ -91,7 +92,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 6318918..268655e 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -18,6 +18,7 @@
#define _SOC_DEVICE_NVS_H_
#include <stdint.h>
+#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
@@ -59,6 +60,6 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
#endif /* _SOC_DEVICE_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index c7bfb65..71e359a 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -18,6 +18,7 @@
#define _SOC_GPIO_H_
#include <stdint.h>
+#include <compiler.h>
#include <arch/io.h>
#include <soc/gpio_defs.h>
#include <soc/iomap.h>
@@ -392,7 +393,7 @@ struct soc_gpio_map {
u32 wake_mask:1;
u32 is_gpio:1;
u32 skip_config:1;
-} __attribute__ ((packed));
+} __packed;
struct soc_gpio_config {
const struct soc_gpio_map *north;
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index d3dfd28..98152e4 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -18,6 +18,7 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
+#include <compiler.h>
#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
@@ -68,7 +69,7 @@ typedef struct {
/* LPSS (0x1000) */
device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 3d11330..546e113 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -208,6 +208,7 @@
#define TCO_TMR 0x70
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+#include <compiler.h>
/* Track power state from reset to log events. */
struct chipset_power_state {
@@ -221,7 +222,7 @@ struct chipset_power_state {
uint32_t gen_pmcon1;
uint32_t gen_pmcon2;
int prev_sleep_state;
-} __attribute__((packed));
+} __packed;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 01fe773..277918e 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -14,6 +14,7 @@
*/
/* This file is derived from the flashrom project. */
+#include <compiler.h>
#include <arch/io.h>
#include <bootstate.h>
#include <console/console.h>
@@ -78,7 +79,7 @@ typedef struct ich9_spi_regs {
uint16_t preop;
uint16_t optype;
uint8_t opmenu[8];
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index a436a4c..15240d1 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
#define _BROADWELL_DEVICE_NVS_H_
#include <stdint.h>
+#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
@@ -35,6 +36,6 @@ typedef struct {
u8 enable[9];
u32 bar0[9];
u32 bar1[9];
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
#endif
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
index 7345df5..a76941b 100644
--- a/src/soc/intel/broadwell/include/soc/gpio.h
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -17,6 +17,7 @@
#define _BROADWELL_GPIO_H_
#include <stdint.h>
+#include <compiler.h>
/* PCH-LP GPIOBASE Registers */
#define GPIO_OWNER(set) (0x00 + ((set) * 4))
@@ -164,7 +165,7 @@ struct gpio_config {
u8 reset;
u8 blink;
u8 pirq;
-} __attribute__ ((packed));
+} __packed;
/* Configure GPIOs with mainboard provided settings */
void init_one_gpio(int gpio_num, struct gpio_config *config);
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index db68b46..1092280 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -16,6 +16,7 @@
#ifndef _BROADWELL_ME_H_
#define _BROADWELL_ME_H_
+#include <compiler.h>
#include <commonlib/loglevel.h>
#define ME_RETRY 100000 /* 1 second */
@@ -75,7 +76,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +86,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -104,7 +105,7 @@ struct me_did {
u32 rapid_start: 1;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
/*
* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
@@ -195,7 +196,7 @@ struct me_hfs2 {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HFS5 0x68
@@ -212,7 +213,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -233,7 +234,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -251,7 +252,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GLOBAL_RESET 0x0b
@@ -274,7 +275,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -285,7 +286,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
/* ICC Messages */
#define ICC_SET_CLOCK_ENABLES 0x3
@@ -297,14 +298,14 @@ struct icc_header {
u32 icc_status;
u32 length;
u32 reserved;
-} __attribute__ ((packed));
+} __packed;
struct icc_clock_enables_msg {
u32 clock_enables;
u32 clock_mask;
u32 no_response: 1;
u32 reserved: 31;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
@@ -318,7 +319,7 @@ struct icc_clock_enables_msg {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -364,21 +365,21 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
typedef struct {
u32 major_version : 16;
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u32 full_net : 1;
@@ -400,13 +401,13 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mbp_mefwcaps;
+} __packed mbp_mefwcaps;
typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -424,7 +425,7 @@ typedef struct {
u32 image_type: 4;
u32 brand: 4;
u32 rsvd1: 16;
-} __attribute__ ((packed)) mbp_me_firmware_type;
+} __packed mbp_me_firmware_type;
typedef struct {
mbp_me_firmware_type rule_data;
@@ -434,7 +435,7 @@ typedef struct {
typedef struct {
u16 icc_start_address;
u16 mask;
-} __attribute__ ((packed)) icc_address_mask;
+} __packed icc_address_mask;
typedef struct {
u8 num_icc_profiles;
@@ -443,7 +444,7 @@ typedef struct {
u8 reserved;
u32 icc_reg_bundles;
icc_address_mask icc_address_mask[0];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u16 lock_state : 1;
@@ -452,24 +453,24 @@ typedef struct {
u16 flash_wear_out : 1;
u16 flash_variable_security : 1;
u16 reserved : 11;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) mbp_at_state;
+} __packed mbp_at_state;
typedef struct {
u32 wake_event_mrst_time_ms;
u32 mrst_pltrst_time_ms;
u32 pltrst_cpurst_time_ms;
-} __attribute__ ((packed)) mbp_plat_time;
+} __packed mbp_plat_time;
typedef struct {
u32 device_type : 2;
u32 reserved : 30;
-} __attribute__ ((packed)) mbp_nfc_data;
+} __packed mbp_nfc_data;
typedef struct {
mbp_fw_version_name *fw_version_name;
@@ -489,7 +490,7 @@ struct me_fwcaps {
u8 length;
mbp_mefwcaps caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 202c56a..7c5677e 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -17,6 +17,7 @@
#ifndef _BROADWELL_NVS_H_
#define _BROADWELL_NVS_H_
+#include <compiler.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
@@ -56,7 +57,7 @@ typedef struct {
/* Device specific (0x1000) */
device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h
index e614718..e13d529 100644
--- a/src/soc/intel/broadwell/include/soc/pei_data.h
+++ b/src/soc/intel/broadwell/include/soc/pei_data.h
@@ -30,6 +30,7 @@
#define PEI_DATA_H
#include <types.h>
+#include <compiler.h>
#include <memory_info.h>
#define PEI_VERSION 22
@@ -74,7 +75,7 @@ struct usb2_port_setting {
uint8_t enable;
uint8_t oc_pin;
uint8_t location;
-} __attribute__((packed));
+} __packed;
struct usb3_port_setting {
uint8_t enable;
@@ -84,7 +85,7 @@ struct usb3_port_setting {
* Set to 1 if trace length is <= 5 inches
*/
uint8_t fixed_eq;
-} __attribute__((packed));
+} __packed;
struct pei_data
{
@@ -192,7 +193,7 @@ struct pei_data
void *data_to_save;
int data_to_save_size;
struct memory_info meminfo;
-} __attribute__((packed));
+} __packed;
typedef struct pei_data PEI_DATA;
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index a5247c4..474ee4e 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -17,13 +17,14 @@
#define _BROADWELL_SMM_H_
#include <stdint.h>
+#include <compiler.h>
#include <cpu/x86/msr.h>
struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
struct smm_relocation_params {
u32 smram_base;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index e07b425..1151ae6 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <bootstate.h>
#include <delay.h>
+#include <compiler.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
@@ -90,7 +91,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
index 1558cc5..857642b 100644
--- a/src/soc/intel/common/gma.h
+++ b/src/soc/intel/common/gma.h
@@ -19,6 +19,7 @@
#define _COMMON_GMA_H_
#include <types.h>
+#include <compiler.h>
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
@@ -36,7 +37,7 @@ typedef struct {
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
+} __packed opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
@@ -73,7 +74,7 @@ typedef struct {
u32 cnot;
u32 nrdy;
u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
+} __packed opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
@@ -81,7 +82,7 @@ typedef struct {
u32 parm;
u32 dslp;
u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
+} __packed opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
@@ -100,7 +101,7 @@ typedef struct {
u32 ccdv;
u32 pcft;
u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
+} __packed opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
@@ -112,7 +113,7 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
+} __packed opregion_vbt_t;
/* IGD OpRegion */
typedef struct {
@@ -121,7 +122,7 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
+} __packed igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
@@ -130,7 +131,7 @@ typedef struct {
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
+} __packed optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
@@ -147,7 +148,7 @@ typedef struct {
u8 codetype;
u8 indicator;
u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
+} __packed optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
@@ -171,7 +172,7 @@ typedef struct {
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
+} __packed optionrom_vbt_t;
#endif /* _COMMON_GMA_H_ */
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c
index a9bbbb3..e5c5a19 100644
--- a/src/soc/intel/common/lpss_i2c.c
+++ b/src/soc/intel/common/lpss_i2c.c
@@ -58,7 +58,7 @@ struct lpss_i2c_regs {
uint32_t rx_level;
uint32_t sda_hold;
uint32_t tx_abort_source;
-} __attribute__((packed));
+} __packed;
/* Use a ~2ms timeout for various operations */
#define LPSS_I2C_TIMEOUT_US 2000
diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c
index 87d8e5c..2b0500a 100644
--- a/src/soc/intel/common/mma.c
+++ b/src/soc/intel/common/mma.c
@@ -37,7 +37,7 @@
struct mma_data_container {
u32 mma_signature; // "MMAD"
u8 mma_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
+} __packed;
/*
Format of the MMA test metadata file, stored under CBFS
diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h
index 9b14c1e..622e111 100644
--- a/src/soc/intel/common/mrc_cache.h
+++ b/src/soc/intel/common/mrc_cache.h
@@ -26,7 +26,7 @@ struct mrc_saved_data {
uint32_t checksum;
uint32_t version;
uint8_t data[0];
-} __attribute__((packed));
+} __packed;
/* Locate the most recently saved MRC data. */
int mrc_cache_get_current(const struct mrc_saved_data **cache);
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
index 5c4e49b..5bafea6 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
#define _BAYTRAIL_DEVICE_NVS_H_
#include <stdint.h>
+#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
@@ -59,6 +60,6 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
#endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 165443e..02c226b 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -17,6 +17,7 @@
#define _BAYTRAIL_GPIO_H_
#include <stdint.h>
+#include <compiler.h>
#include <arch/io.h>
#include <soc/iomap.h>
@@ -328,7 +329,7 @@ struct soc_gpio_map {
u32 smi : 1;
u32 is_gpio : 1;
u32 sci : 1;
-} __attribute__ ((packed));
+} __packed;
struct soc_gpio_config {
const struct soc_gpio_map *ncore;
diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h
index 17c60dd..f0bf888 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/nvs.h
@@ -17,6 +17,7 @@
#ifndef _BAYTRAIL_NVS_H_
#define _BAYTRAIL_NVS_H_
+#include <compiler.h>
#include <soc/device_nvs.h>
typedef struct {
@@ -62,7 +63,7 @@ typedef struct {
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index d5b1c44..9bafdc2 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -17,6 +17,7 @@
#ifndef _BAYTRAIL_PMC_H_
#define _BAYTRAIL_PMC_H_
+#include <compiler.h>
#include <arch/acpi.h>
#define IOCOM1 0x3f8
@@ -264,7 +265,7 @@ struct chipset_power_state {
uint32_t prsts;
uint32_t gen_pmcon1;
uint32_t gen_pmcon2;
-} __attribute__((packed));
+} __packed;
/* Power Management Utility Functions. */
uint16_t get_pmbase(void);
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 1b85fc5..ca42139 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <string.h>
#include <delay.h>
+#include <compiler.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
@@ -90,7 +91,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c
index f98ab97..73ecd71 100644
--- a/src/soc/intel/fsp_broadwell_de/spi.c
+++ b/src/soc/intel/fsp_broadwell_de/spi.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <string.h>
#include <delay.h>
+#include <compiler.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
@@ -89,7 +90,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h
index 5328e76..c177c86 100644
--- a/src/soc/intel/quark/include/soc/pei_wrapper.h
+++ b/src/soc/intel/quark/include/soc/pei_wrapper.h
@@ -53,7 +53,7 @@ struct pei_data {
/* Data from MRC that should be saved to flash */
void *data_to_save;
int data_to_save_size;
-} __attribute__((packed));
+} __packed;
typedef struct pei_data PEI_DATA;
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
index 30d8841..e4c91ec 100644
--- a/src/soc/intel/quark/include/soc/pm.h
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -22,7 +22,7 @@
struct chipset_power_state {
uint32_t prev_sleep_state;
-} __attribute__ ((packed));
+} __packed;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/sch/nvs.h b/src/soc/intel/sch/nvs.h
index 88c4998..6bace94 100644
--- a/src/soc/intel/sch/nvs.h
+++ b/src/soc/intel/sch/nvs.h
@@ -133,7 +133,7 @@ typedef struct {
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t * gnvs);
diff --git a/src/soc/intel/sch/raminit.h b/src/soc/intel/sch/raminit.h
index 4a81ec1..896fd36 100644
--- a/src/soc/intel/sch/raminit.h
+++ b/src/soc/intel/sch/raminit.h
@@ -171,7 +171,7 @@ struct sys_info {
u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */
u8 boot_path;
-} __attribute__ ((packed));
+} __packed;
void sdram_initialize(int boot_mode);
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h
index 79b516d..02c9e65 100644
--- a/src/soc/intel/skylake/include/soc/device_nvs.h
+++ b/src/soc/intel/skylake/include/soc/device_nvs.h
@@ -18,6 +18,7 @@
#define _SOC_DEVICE_NVS_H_
#include <stdint.h>
+#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
@@ -38,6 +39,6 @@ typedef struct {
u8 enable[11];
u32 bar0[11];
u32 bar1[11];
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
#endif
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 49d60b0..e72efc6 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -16,6 +16,7 @@
#ifndef _SOC_FLASH_CONTROLLER__H_
#define _SOC_FLASH_CONTROLLER__H_
+#include <compiler.h>
#include <rules.h>
#include <arch/io.h>
#include <console/console.h>
@@ -165,7 +166,7 @@ typedef struct pch_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) pch_spi_regs;
+} __packed pch_spi_regs;
enum {
HSFS_FDONE = 0x0001,
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index 423e9d1..4000805 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -18,6 +18,8 @@
#ifndef _SKYLAKE_ME_H_
#define _SKYLAKE_ME_H_
+#include <compiler.h>
+
/*
* Management Engine PCI registers
*/
@@ -66,7 +68,7 @@ struct me_hfs {
u32 current_power_source: 2;
u32 d3_support_valid: 1;
u32 d0i3_support_valid: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HFSTS2 0x48
/* Infrastructure Progress Values */
@@ -161,7 +163,7 @@ struct me_hfs2 {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HFSTS3 0x60
#define ME_HFS3_FW_SKU_CONSUMER 0x2
@@ -175,7 +177,7 @@ struct me_hfs3 {
u32 reserved2: 21;
u32 encrypt_key_override: 1;
u32 power_down_mitigation: 1;
-} __attribute__ ((packed));
+} __packed;
void intel_me_status(void);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index f9d5b71..2db5b29 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -18,6 +18,7 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
+#include <compiler.h>
#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h>
@@ -58,7 +59,7 @@ typedef struct {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#if ENV_SMM
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index be8ba79..5848583 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -31,6 +31,7 @@
#define _PEI_DATA_H_
#include <types.h>
+#include <compiler.h>
#define PEI_VERSION 22
@@ -92,7 +93,7 @@ struct pei_data {
void *data_to_save;
int data_to_save_size;
int mem_cfg_id;
-} __attribute__((packed));
+} __packed;
typedef struct pei_data PEI_DATA;
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index d1aa0b4..2717f1f 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -17,6 +17,7 @@
#ifndef _SOC_PM_H_
#define _SOC_PM_H_
+#include <compiler.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <soc/pmc.h>
@@ -146,7 +147,7 @@ struct chipset_power_state {
uint32_t gen_pmcon_b;
uint32_t gblrst_cause[2];
uint32_t prev_sleep_state;
-} __attribute__ ((packed));
+} __packed;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46..5a36ee7 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -18,6 +18,7 @@
#define _SOC_SMM_H_
#include <stdint.h>
+#include <compiler.h>
#include <cpu/x86/msr.h>
#include <fsp/memmap.h>
#include <fsp/romstage.h>
@@ -27,7 +28,7 @@ struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
struct smm_relocation_params {
u32 smram_base;
diff --git a/src/soc/marvell/armada38x/uart.c b/src/soc/marvell/armada38x/uart.c
index c2800d0..041b693 100644
--- a/src/soc/marvell/armada38x/uart.c
+++ b/src/soc/marvell/armada38x/uart.c
@@ -41,7 +41,7 @@ struct armada38x_uart {
uint32_t mcr; // Modem control register.
uint32_t lsr; // Line status register.
uint32_t msr; // Modem status register.
-} __attribute__ ((packed));
+} __packed;
static void armada38x_uart_tx_flush(struct armada38x_uart *uart_ptr);
static int armada38x_uart_tst_byte(struct armada38x_uart *uart_ptr);
diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c
index adc8074..d0b140d 100644
--- a/src/soc/mediatek/mt8173/uart.c
+++ b/src/soc/mediatek/mt8173/uart.c
@@ -19,6 +19,7 @@
#include <console/uart.h>
#include <drivers/uart/uart8250reg.h>
#include <stdint.h>
+#include <compiler.h>
#include <soc/addressmap.h>
@@ -56,7 +57,7 @@ struct mtk_uart {
};
uint32_t autobaud_en; /* Enable auto baudrate. */
uint32_t highspeed; /* High speed UART. */
-} __attribute__ ((packed));
+} __packed;
/* Peripheral Reset and Power Down registers */
struct mtk_peri_globalcon {
@@ -75,7 +76,7 @@ struct mtk_peri_globalcon {
uint32_t pdn_md1_sta;
uint32_t pdn_md2_sta;
uint32_t pdn_md_mask;
-} __attribute__ ((packed));
+} __packed;
static struct mtk_uart *const uart_ptr = (void *)UART0_BASE;
diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h
index f7d78ee..165b823 100644
--- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h
@@ -14,8 +14,10 @@
#ifndef _TEGRA124_CLK_RST_H_
#define _TEGRA124_CLK_RST_H_
+#include <compiler.h>
+
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-struct __attribute__ ((__packed__)) clk_rst_ctlr {
+struct __packed clk_rst_ctlr {
u32 rst_src; /* _RST_SOURCE, 0x000 */
u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */
u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */
diff --git a/src/soc/nvidia/tegra124/include/soc/dma.h b/src/soc/nvidia/tegra124/include/soc/dma.h
index 53edc92..4d3e9f6 100644
--- a/src/soc/nvidia/tegra124/include/soc/dma.h
+++ b/src/soc/nvidia/tegra124/include/soc/dma.h
@@ -17,6 +17,7 @@
#define __NVIDIA_TEGRA124_DMA_H__
#include <inttypes.h>
+#include <compiler.h>
#include <soc/addressmap.h>
/*
@@ -66,7 +67,7 @@ struct apb_dma {
u32 chan_wt_reg2; /* 0x4c */
u32 chan_wr_reg3; /* 0x50 */
u32 channel_swid1; /* 0x54 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma, channel_swid1, 0x54);
/*
@@ -164,7 +165,7 @@ struct apb_dma_channel_regs {
u32 apb_seq; /* 0x1c */
u32 wcount; /* 0x20 */
u32 word_transfer; /* 0x24 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma_channel_regs, word_transfer, 0x24);
struct apb_dma_channel {
diff --git a/src/soc/nvidia/tegra124/include/soc/emc.h b/src/soc/nvidia/tegra124/include/soc/emc.h
index bae0068..f1ff7f3 100644
--- a/src/soc/nvidia/tegra124/include/soc/emc.h
+++ b/src/soc/nvidia/tegra124/include/soc/emc.h
@@ -17,6 +17,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <compiler.h>
enum {
EMC_PIN_RESET_MASK = 1 << 8,
@@ -313,7 +314,7 @@ struct tegra_emc_regs {
uint32_t puterm_width; /* 0x56c */
uint32_t bgbias_ctl0; /* 0x570 */
uint32_t puterm_adj; /* 0x574 */
-} __attribute__((packed));
+} __packed;
check_member(tegra_emc_regs, puterm_adj, 0x574);
diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h
index a9ea4ea..c56b302 100644
--- a/src/soc/nvidia/tegra124/include/soc/spi.h
+++ b/src/soc/nvidia/tegra124/include/soc/spi.h
@@ -17,6 +17,7 @@
#include <spi-generic.h>
#include <soc/dma.h>
#include <stddef.h>
+#include <compiler.h>
struct tegra_spi_regs {
u32 command1; /* 0x000: SPI_COMMAND1 */
@@ -34,7 +35,7 @@ struct tegra_spi_regs {
u32 rsvd2[31]; /* 0x10c-0x187 reserved */
u32 rx_fifo; /* 0x188: SPI_FIFO2 */
u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
-} __attribute__((packed));
+} __packed;
check_member(tegra_spi_regs, spare_ctl, 0x18c);
enum spi_xfer_mode {
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 8a0d038..6a16eb2 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -13,6 +13,7 @@
*/
#include <stdint.h>
+#include <compiler.h>
/* Function unit addresses. */
enum {
@@ -642,7 +643,7 @@ struct lp0_header {
uint32_t destination; // Where to load the blob in iRAM.
uint32_t entry_point; // Entry point for the blob.
uint32_t code_length; // Length of just the data.
-} __attribute__((packed));
+} __packed;
struct lp0_header header __attribute__((section(".header"))) =
{
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 1d4934b..76ea426 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/console.h> /* for __console definition */
@@ -38,7 +39,7 @@ struct tegra124_uart {
uint32_t mcr; // Modem control register.
uint32_t lsr; // Line status register.
uint32_t msr; // Modem status register.
-} __attribute__ ((packed));
+} __packed;
static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr);
static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr);
diff --git a/src/soc/nvidia/tegra132/include/soc/clk_rst.h b/src/soc/nvidia/tegra132/include/soc/clk_rst.h
index 46ab745..6a34b55 100644
--- a/src/soc/nvidia/tegra132/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra132/include/soc/clk_rst.h
@@ -15,9 +15,10 @@
#define _TEGRA132_CLK_RST_H_
#include <stdint.h>
#include <stddef.h>
+#include <compiler.h>
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-struct __attribute__ ((__packed__)) clk_rst_ctlr {
+struct __packed clk_rst_ctlr {
u32 rst_src; /* _RST_SOURCE, 0x000 */
u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */
u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */
diff --git a/src/soc/nvidia/tegra132/include/soc/clst_clk.h b/src/soc/nvidia/tegra132/include/soc/clst_clk.h
index 0d5f681..fce7361 100644
--- a/src/soc/nvidia/tegra132/include/soc/clst_clk.h
+++ b/src/soc/nvidia/tegra132/include/soc/clst_clk.h
@@ -14,8 +14,9 @@
#ifndef _TEGRA132_CLST_CLK_H_
#define _TEGRA132_CLST_CLK_H_
+#include <compiler.h>
/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */
-struct __attribute__ ((__packed__)) clst_clk_ctlr {
+struct __packed clst_clk_ctlr {
u32 pllx_base; /* _PLLX_BASE, 0x000 */
u32 pllx_misc; /* _PLLX_MISC, 0x004 */
u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */
diff --git a/src/soc/nvidia/tegra132/include/soc/dma.h b/src/soc/nvidia/tegra132/include/soc/dma.h
index e3beada..14d723c 100644
--- a/src/soc/nvidia/tegra132/include/soc/dma.h
+++ b/src/soc/nvidia/tegra132/include/soc/dma.h
@@ -17,6 +17,7 @@
#define __NVIDIA_TEGRA132_DMA_H__
#include <inttypes.h>
+#include <compiler.h>
#include <soc/addressmap.h>
/*
@@ -66,7 +67,7 @@ struct apb_dma {
u32 chan_wt_reg2; /* 0x4c */
u32 chan_wr_reg3; /* 0x50 */
u32 channel_swid1; /* 0x54 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma, channel_swid1, 0x54);
/*
@@ -164,7 +165,7 @@ struct apb_dma_channel_regs {
u32 apb_seq; /* 0x1c */
u32 wcount; /* 0x20 */
u32 word_transfer; /* 0x24 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma_channel_regs, word_transfer, 0x24);
struct apb_dma_channel {
diff --git a/src/soc/nvidia/tegra132/include/soc/emc.h b/src/soc/nvidia/tegra132/include/soc/emc.h
index 6ede4e0..948ba6c 100644
--- a/src/soc/nvidia/tegra132/include/soc/emc.h
+++ b/src/soc/nvidia/tegra132/include/soc/emc.h
@@ -17,6 +17,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <compiler.h>
enum {
EMC_PIN_RESET_MASK = 1 << 8,
@@ -313,7 +314,7 @@ struct tegra_emc_regs {
uint32_t puterm_width; /* 0x56c */
uint32_t bgbias_ctl0; /* 0x570 */
uint32_t puterm_adj; /* 0x574 */
-} __attribute__((packed));
+} __packed;
check_member(tegra_emc_regs, puterm_adj, 0x574);
diff --git a/src/soc/nvidia/tegra132/include/soc/spi.h b/src/soc/nvidia/tegra132/include/soc/spi.h
index d286b32..f05d1a8 100644
--- a/src/soc/nvidia/tegra132/include/soc/spi.h
+++ b/src/soc/nvidia/tegra132/include/soc/spi.h
@@ -18,6 +18,7 @@
#include <soc/dma.h>
#include <spi-generic.h>
#include <stddef.h>
+#include <compiler.h>
struct tegra_spi_regs {
u32 command1; /* 0x000: SPI_COMMAND1 */
@@ -35,7 +36,7 @@ struct tegra_spi_regs {
u32 rsvd2[31]; /* 0x10c-0x187 reserved */
u32 rx_fifo; /* 0x188: SPI_FIFO2 */
u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
-} __attribute__((packed));
+} __packed;
check_member(tegra_spi_regs, spare_ctl, 0x18c);
enum spi_xfer_mode {
diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index 94d2263..7610cef 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -13,6 +13,7 @@
*/
#include <stdint.h>
+#include <compiler.h>
/* Function unit addresses. */
enum {
@@ -675,7 +676,7 @@ struct lp0_header {
uint32_t destination; // Where to load the blob in iRAM.
uint32_t entry_point; // Entry point for the blob.
uint32_t code_length; // Length of just the data.
-} __attribute__((packed));
+} __packed;
struct lp0_header header __attribute__((section(".header"))) =
{
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index a530e2d..5ef16b8 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -19,6 +19,7 @@
#include <console/uart.h>
#include <drivers/uart/uart8250reg.h>
#include <stdint.h>
+#include <compiler.h>
/*
* TODO: Use DRIVERS_UART_8250MEM driver instead.
@@ -44,7 +45,7 @@ struct tegra132_uart {
uint32_t mcr; // Modem control register.
uint32_t lsr; // Line status register.
uint32_t msr; // Modem status register.
-} __attribute__ ((packed));
+} __packed;
static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr);
static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr);
diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
index 9c62e61..65fb8fe 100644
--- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
@@ -15,9 +15,10 @@
#define _TEGRA210_CLK_RST_H_
#include <stdint.h>
#include <stddef.h>
+#include <compiler.h>
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-struct __attribute__ ((__packed__)) clk_rst_ctlr {
+struct __packed clk_rst_ctlr {
u32 rst_src; /* _RST_SOURCE, 0x000 */
u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */
u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */
diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h
index 89690f8..48ea168 100644
--- a/src/soc/nvidia/tegra210/include/soc/clst_clk.h
+++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h
@@ -15,7 +15,7 @@
#define _TEGRA210_CLST_CLK_H_
/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */
-struct __attribute__ ((__packed__)) clst_clk_ctlr {
+struct __packed clst_clk_ctlr {
u32 pllx_base; /* _PLLX_BASE, 0x000 */
u32 pllx_misc; /* _PLLX_MISC, 0x004 */
u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */
diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h
index 66db52a..a4a9213 100644
--- a/src/soc/nvidia/tegra210/include/soc/dma.h
+++ b/src/soc/nvidia/tegra210/include/soc/dma.h
@@ -16,6 +16,7 @@
#define __NVIDIA_TEGRA210_DMA_H__
#include <inttypes.h>
+#include <compiler.h>
#include <soc/addressmap.h>
/*
@@ -65,7 +66,7 @@ struct apb_dma {
u32 chan_wt_reg2; /* 0x4c */
u32 chan_wr_reg3; /* 0x50 */
u32 channel_swid1; /* 0x54 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma, channel_swid1, 0x54);
/* Security enable for DMA channel */
@@ -166,7 +167,7 @@ struct apb_dma_channel_regs {
u32 apb_seq; /* 0x1c */
u32 wcount; /* 0x20 */
u32 word_transfer; /* 0x24 */
-} __attribute__((packed));
+} __packed;
check_member(apb_dma_channel_regs, word_transfer, 0x24);
struct apb_dma_channel {
diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h
index 09bc7c6..3c95efa 100644
--- a/src/soc/nvidia/tegra210/include/soc/emc.h
+++ b/src/soc/nvidia/tegra210/include/soc/emc.h
@@ -465,7 +465,7 @@ struct tegra_emc_regs {
uint32_t pmacro_ib_rxrt; /* 0xCF4 */
uint32_t pmacro_training_ctrl0; /* 0xCF8 */
uint32_t pmacro_training_ctrl1; /* 0xCFC */
-} __attribute__((packed));
+} __packed;
check_member(tegra_emc_regs, pmacro_training_ctrl1, 0xCFC);
diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h
index 49f7868..f0f9340 100644
--- a/src/soc/nvidia/tegra210/include/soc/spi.h
+++ b/src/soc/nvidia/tegra210/include/soc/spi.h
@@ -18,6 +18,7 @@
#include <soc/dma.h>
#include <spi-generic.h>
#include <stddef.h>
+#include <compiler.h>
struct tegra_spi_regs {
u32 command1; /* 0x000: SPI_COMMAND1 */
@@ -35,7 +36,7 @@ struct tegra_spi_regs {
u32 rsvd2[31]; /* 0x10c-0x187 reserved */
u32 rx_fifo; /* 0x188: SPI_FIFO2 */
u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
-} __attribute__((packed));
+} __packed;
check_member(tegra_spi_regs, spare_ctl, 0x18c);
enum spi_xfer_mode {
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 15477d6..12cd648 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -1118,7 +1118,7 @@ struct lp0_header {
uint32_t destination; // Where to load the blob in iRAM.
uint32_t entry_point; // Entry point for the blob.
uint32_t code_length; // Length of just the data.
-} __attribute__((packed));
+} __packed;
struct lp0_header header __attribute__((section(".header"))) =
{
diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c
index 1f16067..c0a6654 100644
--- a/src/soc/nvidia/tegra210/uart.c
+++ b/src/soc/nvidia/tegra210/uart.c
@@ -38,7 +38,7 @@ struct tegra210_uart {
uint32_t mcr; // Modem control register.
uint32_t lsr; // Line status register.
uint32_t msr; // Modem status register.
-} __attribute__ ((packed));
+} __packed;
static struct tegra210_uart * const uart_ptr =
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h
index e5ea828..14b5b91 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h
@@ -32,6 +32,7 @@
#define _IPQ40XX_CDP_H_
#include <types.h>
+#include <compiler.h>
unsigned smem_get_board_machtype(void);
@@ -148,7 +149,7 @@ typedef struct {
flash_desc flashdesc;
spinorflash_params_t flash_param;
#endif
-} __attribute__ ((__packed__)) board_ipq40xx_params_t;
+} __packed board_ipq40xx_params_t;
extern board_ipq40xx_params_t *gboard_param;
diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c
index da9d5ae..caddf19 100644
--- a/src/soc/qualcomm/ipq40xx/lcc.c
+++ b/src/soc/qualcomm/ipq40xx/lcc.c
@@ -43,11 +43,11 @@ typedef struct {
void *lcc_pll_regs;
} IpqLccClocks;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t apcs;
} IpqLccGccRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t mode;
uint32_t l_val;
uint32_t m_val;
@@ -57,20 +57,20 @@ typedef struct __attribute__((packed)) {
uint32_t status;
} IpqLccPll0Regs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t ns;
uint32_t md;
uint32_t UNUSED;
uint32_t status;
} IpqLccAhbixRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t ns;
uint32_t md;
uint32_t status;
} IpqLccMi2sRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t pri;
uint32_t sec;
} IpqLccPllRegs;
diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h
index b7498ce..bdfeb89 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h
@@ -5,6 +5,7 @@
#define _IPQ806X_CDP_H_
#include <types.h>
+#include <compiler.h>
unsigned smem_get_board_machtype(void);
@@ -123,7 +124,7 @@ typedef struct {
flash_desc flashdesc;
spinorflash_params_t flash_param;
#endif
-} __attribute__ ((__packed__)) board_ipq806x_params_t;
+} __packed board_ipq806x_params_t;
extern board_ipq806x_params_t *gboard_param;
diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c
index d577487..2dfd291 100644
--- a/src/soc/qualcomm/ipq806x/lcc.c
+++ b/src/soc/qualcomm/ipq806x/lcc.c
@@ -30,6 +30,7 @@
#include <stdlib.h>
#include <stdint.h>
#include <delay.h>
+#include <compiler.h>
#include <console/console.h>
#include <soc/clock.h>
#include <soc/lcc-reg.h>
@@ -43,11 +44,11 @@ typedef struct {
void *lcc_pll_regs;
} Ipq806xLccClocks;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t apcs;
} Ipq806xLccGccRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t mode;
uint32_t l_val;
uint32_t m_val;
@@ -57,20 +58,20 @@ typedef struct __attribute__((packed)) {
uint32_t status;
} Ipq806xLccPll0Regs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t ns;
uint32_t md;
uint32_t UNUSED;
uint32_t status;
} Ipq806xLccAhbixRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t ns;
uint32_t md;
uint32_t status;
} Ipq806xLccMi2sRegs;
-typedef struct __attribute__((packed)) {
+typedef struct __packed {
uint32_t pri;
uint32_t sec;
} Ipq806xLccPllRegs;
diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c
index 97db093..5ead741 100644
--- a/src/soc/samsung/exynos5250/i2c.c
+++ b/src/soc/samsung/exynos5250/i2c.c
@@ -18,12 +18,13 @@
#include <assert.h>
#include <console/console.h>
#include <delay.h>
+#include <compiler.h>
#include <device/i2c.h>
#include <soc/clk.h>
#include <soc/i2c.h>
#include <soc/periph.h>
-struct __attribute__ ((packed)) i2c_regs
+struct __packed i2c_regs
{
uint8_t con;
uint8_t _1[3];
diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h
index 14553f9..dbcc4fe 100644
--- a/src/soc/samsung/exynos5250/include/soc/power.h
+++ b/src/soc/samsung/exynos5250/include/soc/power.h
@@ -18,6 +18,7 @@
#ifndef CPU_SAMSUNG_EXYNOS5250_POWER_H
#define CPU_SAMSUNG_EXYNOS5250_POWER_H
+#include <compiler.h>
#include <soc/cpu.h>
/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
@@ -59,7 +60,7 @@ struct exynos5_power {
uint32_t padret_uart_opt; /* 0x3128 */
uint8_t reserved8[0x1e0];
uint32_t ps_hold_ctrl; /* 0x330c */
-} __attribute__ ((__packed__));
+} __packed;
check_member(exynos5_power, ps_hold_ctrl, 0x330c);
static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c
index 877afab..78d36c5 100644
--- a/src/soc/samsung/exynos5420/i2c.c
+++ b/src/soc/samsung/exynos5420/i2c.c
@@ -24,9 +24,10 @@
#include <soc/periph.h>
#include <soc/pinmux.h>
#include <stddef.h>
+#include <compiler.h>
#include <timer.h>
-struct __attribute__ ((packed)) i2c_regs
+struct __packed i2c_regs
{
uint8_t con;
uint8_t _1[3];
@@ -40,7 +41,7 @@ struct __attribute__ ((packed)) i2c_regs
uint8_t _5[3];
};
-struct __attribute__ ((packed)) hsi2c_regs
+struct __packed hsi2c_regs
{
uint32_t usi_ctl;
uint32_t usi_fifo_ctl;
diff --git a/src/soc/samsung/exynos5420/include/soc/dmc.h b/src/soc/samsung/exynos5420/include/soc/dmc.h
index ef0198c..2ea415a 100644
--- a/src/soc/samsung/exynos5420/include/soc/dmc.h
+++ b/src/soc/samsung/exynos5420/include/soc/dmc.h
@@ -68,6 +68,7 @@
#ifndef __ASSEMBLER__
+#include <compiler.h>
#include <soc/cpu.h>
struct exynos5_dmc {
@@ -201,7 +202,7 @@ struct exynos5_dmc {
uint32_t pmcnt2_ppc;
uint8_t res41[0xc];
uint32_t pmcnt3_ppc; /* 0xe140 */
-} __attribute__((packed));
+} __packed;
check_member(exynos5_dmc, pmcnt3_ppc, 0xe140);
static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0;
@@ -252,7 +253,7 @@ struct exynos5_phy_control {
uint32_t phy_con40;
uint32_t phy_con41;
uint32_t phy_con42;
-} __attribute__((packed));
+} __packed;
check_member(exynos5_phy_control, phy_con42, 0xac);
static struct exynos5_phy_control * const exynos_phy0_control =
@@ -267,7 +268,7 @@ struct exynos5_tzasc {
uint8_t res2[0x8];
uint32_t memconfig0;
uint32_t memconfig1;
-} __attribute__((packed));
+} __packed;
static struct exynos5_tzasc * const exynos_tzasc0 =
(void *)EXYNOS5420_DMC_TZASC_0;
diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h
index 5920916..dd48f73 100644
--- a/src/soc/samsung/exynos5420/include/soc/power.h
+++ b/src/soc/samsung/exynos5420/include/soc/power.h
@@ -19,6 +19,7 @@
#define CPU_SAMSUNG_EXYNOS5420_POWER_H
#include <soc/cpu.h>
+#include <compiler.h>
/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
void power_enable_hw_thermal_trip(void);
@@ -72,7 +73,7 @@ struct exynos5_power {
uint32_t padret_dram_cblk_opt; /* 0x31e8 */
uint8_t reservedC[0x120];
uint32_t ps_hold_ctrl; /* 0x330c */
-} __attribute__ ((__packed__));
+} __packed;
check_member(exynos5_power, ps_hold_ctrl, 0x330c);
static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 6b8d654..f95a0b4 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -17,6 +17,8 @@
#ifndef _INTEL_ME_H
#define _INTEL_ME_H
+#include <compiler.h>
+
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
@@ -75,7 +77,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +87,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -98,7 +100,7 @@ struct me_did {
u32 reserved: 8;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
@@ -124,7 +126,7 @@ struct me_gmes {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
@@ -136,7 +138,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -157,7 +159,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -175,7 +177,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
@@ -198,7 +200,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -209,7 +211,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
@@ -224,7 +226,7 @@ struct me_fw_version {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -254,7 +256,7 @@ typedef struct {
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u8 num_icc_profiles;
@@ -262,7 +264,7 @@ typedef struct {
u8 icc_profile_index;
u8 reserved;
u32 register_lock_mask[3];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u32 full_net : 1;
@@ -285,7 +287,7 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mefwcaps_sku;
+} __packed mefwcaps_sku;
typedef struct {
u16 lock_state : 1;
@@ -296,13 +298,13 @@ typedef struct {
u16 wwan3gpresent : 1;
u16 wwan3goob : 1;
u16 reserved : 9;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) tdt_state_info;
+} __packed tdt_state_info;
typedef struct {
u32 platform_target_usage_type : 4;
@@ -312,7 +314,7 @@ typedef struct {
u32 intel_me_fw_image_type : 4;
u32 platform_brand : 4;
u32 reserved_1 : 16;
-} __attribute__ ((packed)) platform_type_rule_data;
+} __packed platform_type_rule_data;
typedef struct {
mefwcaps_sku fw_capabilities;
@@ -323,7 +325,7 @@ typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -349,20 +351,20 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
struct me_fwcaps {
u32 id;
u8 length;
mefwcaps_sku caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 8775335..390eda3 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -149,7 +149,7 @@ typedef struct {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 7b42b06..8bd3b96 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -17,6 +17,7 @@
#define INTEL_COMMON_GPIO_H
#include <stdint.h>
+#include <compiler.h>
/* LPC GPIO Base Address Register */
#define GPIO_BASE 0x48
@@ -91,7 +92,7 @@ struct pch_gpio_set1 {
u32 gpio29 : 1;
u32 gpio30 : 1;
u32 gpio31 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set2 {
u32 gpio32 : 1;
@@ -126,7 +127,7 @@ struct pch_gpio_set2 {
u32 gpio61 : 1;
u32 gpio62 : 1;
u32 gpio63 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set3 {
u32 gpio64 : 1;
@@ -141,7 +142,7 @@ struct pch_gpio_set3 {
u32 gpio73 : 1;
u32 gpio74 : 1;
u32 gpio75 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_map {
struct {
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1ab151b..4387f92 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
+#include <compiler.h>
#include <bootstate.h>
#include <delay.h>
#include <arch/io.h>
@@ -82,7 +83,7 @@ typedef struct ich7_spi_regs {
uint16_t preop;
uint16_t optype;
uint8_t opmenu[8];
-} __attribute__((packed)) ich7_spi_regs;
+} __packed ich7_spi_regs;
typedef struct ich9_spi_regs {
uint32_t bfpr;
@@ -115,7 +116,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.h b/src/southbridge/intel/fsp_bd82x6x/gpio.h
index d2f0e50..a46a8fe 100644
--- a/src/southbridge/intel/fsp_bd82x6x/gpio.h
+++ b/src/southbridge/intel/fsp_bd82x6x/gpio.h
@@ -69,7 +69,7 @@ struct pch_gpio_set1 {
u32 gpio29 : 1;
u32 gpio30 : 1;
u32 gpio31 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set2 {
u32 gpio32 : 1;
@@ -104,7 +104,7 @@ struct pch_gpio_set2 {
u32 gpio61 : 1;
u32 gpio62 : 1;
u32 gpio63 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set3 {
u32 gpio64 : 1;
@@ -120,7 +120,7 @@ struct pch_gpio_set3 {
u32 gpio74 : 1;
u32 gpio75 : 1;
u32 fill_bitfield : 20;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_map {
union {
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h
index 6b8d654..f95a0b4 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.h
+++ b/src/southbridge/intel/fsp_bd82x6x/me.h
@@ -17,6 +17,8 @@
#ifndef _INTEL_ME_H
#define _INTEL_ME_H
+#include <compiler.h>
+
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
@@ -75,7 +77,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +87,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -98,7 +100,7 @@ struct me_did {
u32 reserved: 8;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
@@ -124,7 +126,7 @@ struct me_gmes {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
@@ -136,7 +138,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -157,7 +159,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -175,7 +177,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
@@ -198,7 +200,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -209,7 +211,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
@@ -224,7 +226,7 @@ struct me_fw_version {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -254,7 +256,7 @@ typedef struct {
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u8 num_icc_profiles;
@@ -262,7 +264,7 @@ typedef struct {
u8 icc_profile_index;
u8 reserved;
u32 register_lock_mask[3];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u32 full_net : 1;
@@ -285,7 +287,7 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mefwcaps_sku;
+} __packed mefwcaps_sku;
typedef struct {
u16 lock_state : 1;
@@ -296,13 +298,13 @@ typedef struct {
u16 wwan3gpresent : 1;
u16 wwan3goob : 1;
u16 reserved : 9;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) tdt_state_info;
+} __packed tdt_state_info;
typedef struct {
u32 platform_target_usage_type : 4;
@@ -312,7 +314,7 @@ typedef struct {
u32 intel_me_fw_image_type : 4;
u32 platform_brand : 4;
u32 reserved_1 : 16;
-} __attribute__ ((packed)) platform_type_rule_data;
+} __packed platform_type_rule_data;
typedef struct {
mefwcaps_sku fw_capabilities;
@@ -323,7 +325,7 @@ typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -349,20 +351,20 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
struct me_fwcaps {
u32 id;
u8 length;
mefwcaps_sku caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h
index 83bc832..a514714 100644
--- a/src/southbridge/intel/fsp_bd82x6x/nvs.h
+++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h
@@ -146,7 +146,7 @@ typedef struct {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_i89xx/gpio.h b/src/southbridge/intel/fsp_i89xx/gpio.h
index ee5484d..95cf70a 100644
--- a/src/southbridge/intel/fsp_i89xx/gpio.h
+++ b/src/southbridge/intel/fsp_i89xx/gpio.h
@@ -69,7 +69,7 @@ struct pch_gpio_set1 {
u32 gpio29 : 1;
u32 gpio30 : 1;
u32 gpio31 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set2 {
u32 gpio32 : 1;
@@ -104,7 +104,7 @@ struct pch_gpio_set2 {
u32 gpio61 : 1;
u32 gpio62 : 1;
u32 gpio63 : 1;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_set3 {
u32 gpio64 : 1;
@@ -120,7 +120,7 @@ struct pch_gpio_set3 {
u32 gpio74 : 1;
u32 gpio75 : 1;
u32 fill_bitfield : 20;
-} __attribute__ ((packed));
+} __packed;
struct pch_gpio_map {
union {
diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h
index 6b8d654..f95a0b4 100644
--- a/src/southbridge/intel/fsp_i89xx/me.h
+++ b/src/southbridge/intel/fsp_i89xx/me.h
@@ -17,6 +17,8 @@
#ifndef _INTEL_ME_H
#define _INTEL_ME_H
+#include <compiler.h>
+
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
@@ -75,7 +77,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +87,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -98,7 +100,7 @@ struct me_did {
u32 reserved: 8;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
@@ -124,7 +126,7 @@ struct me_gmes {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
@@ -136,7 +138,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -157,7 +159,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -175,7 +177,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
@@ -198,7 +200,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -209,7 +211,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
@@ -224,7 +226,7 @@ struct me_fw_version {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -254,7 +256,7 @@ typedef struct {
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u8 num_icc_profiles;
@@ -262,7 +264,7 @@ typedef struct {
u8 icc_profile_index;
u8 reserved;
u32 register_lock_mask[3];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u32 full_net : 1;
@@ -285,7 +287,7 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mefwcaps_sku;
+} __packed mefwcaps_sku;
typedef struct {
u16 lock_state : 1;
@@ -296,13 +298,13 @@ typedef struct {
u16 wwan3gpresent : 1;
u16 wwan3goob : 1;
u16 reserved : 9;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) tdt_state_info;
+} __packed tdt_state_info;
typedef struct {
u32 platform_target_usage_type : 4;
@@ -312,7 +314,7 @@ typedef struct {
u32 intel_me_fw_image_type : 4;
u32 platform_brand : 4;
u32 reserved_1 : 16;
-} __attribute__ ((packed)) platform_type_rule_data;
+} __packed platform_type_rule_data;
typedef struct {
mefwcaps_sku fw_capabilities;
@@ -323,7 +325,7 @@ typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -349,20 +351,20 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
struct me_fwcaps {
u32 id;
u8 length;
mefwcaps_sku caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h
index 83bc832..a514714 100644
--- a/src/southbridge/intel/fsp_i89xx/nvs.h
+++ b/src/southbridge/intel/fsp_i89xx/nvs.h
@@ -146,7 +146,7 @@ typedef struct {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 8a0b578..1a916f4 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -72,14 +72,14 @@ struct soc_gpio {
u32 gpio29 : 1;
u32 gpio30 : 1;
u32 gpio31 : 1;
-} __attribute__ ((packed));
+} __packed;
struct soc_cfio {
u32 pad_conf_0;
u32 pad_conf_1;
u32 pad_val;
u32 pad_dft;
-} __attribute__ ((packed));
+} __packed;
struct soc_gpio_map {
/* GPIO core */
diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h
index 5449f94..12de769 100644
--- a/src/southbridge/intel/fsp_rangeley/nvs.h
+++ b/src/southbridge/intel/fsp_rangeley/nvs.h
@@ -143,7 +143,7 @@ typedef struct {
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 rsvd13[11]; /* 0xf5 - rsvd */
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 007c612..ae4bc26 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <delay.h>
#include <arch/io.h>
+#include <compiler.h>
#include <console/console.h>
#include <device/pci_ids.h>
@@ -71,7 +72,7 @@ typedef struct ich7_spi_regs {
uint16_t preop;
uint16_t optype;
uint8_t opmenu[8];
-} __attribute__((packed)) ich7_spi_regs;
+} __packed ich7_spi_regs;
typedef struct ich9_spi_regs {
uint32_t bfpr; // 0
@@ -104,7 +105,7 @@ typedef struct ich9_spi_regs {
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
typedef struct ich10_spi_regs {
uint32_t bfpr;
@@ -136,7 +137,7 @@ typedef struct ich10_spi_regs {
uint32_t scs;
uint32_t bcr;
uint32_t tcgc;
-} __attribute__((packed)) ich10_spi_regs;
+} __packed ich10_spi_regs;
typedef struct ich_spi_controller {
int locked;
diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h
index 9db504f..3a72f4d 100644
--- a/src/southbridge/intel/i82801dx/nvs.h
+++ b/src/southbridge/intel/i82801dx/nvs.h
@@ -130,4 +130,4 @@ typedef struct {
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index 49c6fc1..c3a3920 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
+
typedef struct {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
@@ -130,6 +132,6 @@ typedef struct {
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index 49c6fc1..660a8f7 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -130,6 +130,6 @@ typedef struct {
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h
index 06495c1..99cfb15 100644
--- a/src/southbridge/intel/ibexpeak/me.h
+++ b/src/southbridge/intel/ibexpeak/me.h
@@ -75,7 +75,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +85,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -98,7 +98,7 @@ struct me_did {
u32 reserved: 8;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
@@ -124,7 +124,7 @@ struct me_gmes {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
@@ -136,7 +136,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -157,7 +157,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -175,7 +175,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
@@ -199,7 +199,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -210,7 +210,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
@@ -225,7 +225,7 @@ struct me_fw_version {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -255,7 +255,7 @@ typedef struct {
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u8 num_icc_profiles;
@@ -263,7 +263,7 @@ typedef struct {
u8 icc_profile_index;
u8 reserved;
u32 register_lock_mask[3];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u32 full_net : 1;
@@ -286,7 +286,7 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mefwcaps_sku;
+} __packed mefwcaps_sku;
typedef struct {
u16 lock_state : 1;
@@ -297,13 +297,13 @@ typedef struct {
u16 wwan3gpresent : 1;
u16 wwan3goob : 1;
u16 reserved : 9;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) tdt_state_info;
+} __packed tdt_state_info;
typedef struct {
u32 platform_target_usage_type : 4;
@@ -313,7 +313,7 @@ typedef struct {
u32 intel_me_fw_image_type : 4;
u32 platform_brand : 4;
u32 reserved_1 : 16;
-} __attribute__ ((packed)) platform_type_rule_data;
+} __packed platform_type_rule_data;
typedef struct {
mefwcaps_sku fw_capabilities;
@@ -324,7 +324,7 @@ typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -350,20 +350,20 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
struct me_fwcaps {
u32 id;
u8 length;
mefwcaps_sku caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index 1c0011a..623acf7 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -148,7 +148,7 @@ typedef struct {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index c35e770..a98542c 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -158,7 +158,7 @@ struct pch_lp_gpio_map {
u8 reset;
u8 blink;
u8 pirq;
-} __attribute__ ((packed));
+} __packed;
/* Configure GPIOs with mainboard provided settings */
void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index 912fb62..a1987eb 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -17,6 +17,8 @@
#ifndef _INTEL_ME_H
#define _INTEL_ME_H
+#include <compiler.h>
+
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
@@ -75,7 +77,7 @@ struct me_hfs {
u32 boot_options_present: 1;
u32 ack_data: 3;
u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_UMA 0x44
@@ -85,7 +87,7 @@ struct me_uma {
u32 valid: 1;
u32 reserved_0: 14;
u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@@ -100,7 +102,7 @@ struct me_did {
u32 rapid_start: 1;
u32 status: 4;
u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
/*
* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
@@ -191,7 +193,7 @@ struct me_hfs2 {
u32 current_state: 8;
u32 current_pmevent: 4;
u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
#define PCI_ME_H_GS2 0x70
#define PCI_ME_MBP_GIVE_UP 0x01
@@ -206,7 +208,7 @@ struct me_heres {
u32 reserved: 26;
u32 extend_feature_present: 1;
u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
/*
* Management Engine MEI registers
@@ -227,7 +229,7 @@ struct mei_csr {
u32 buffer_read_ptr: 8;
u32 buffer_write_ptr: 8;
u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
#define MEI_ADDRESS_CORE 0x01
#define MEI_ADDRESS_AMT 0x02
@@ -245,7 +247,7 @@ struct mei_header {
u32 length: 9;
u32 reserved: 6;
u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_FWCAPS 0x03
@@ -268,7 +270,7 @@ struct mkhi_header {
u32 is_response: 1;
u32 reserved: 8;
u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
struct me_fw_version {
u16 code_minor;
@@ -279,7 +281,7 @@ struct me_fw_version {
u16 recovery_major;
u16 recovery_build_number;
u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
/* ICC Messages */
#define ICC_SET_CLOCK_ENABLES 0x3
@@ -291,14 +293,14 @@ struct icc_header {
u32 icc_status;
u32 length;
u32 reserved;
-} __attribute__ ((packed));
+} __packed;
struct icc_clock_enables_msg {
u32 clock_enables;
u32 clock_mask;
u32 no_response: 1;
u32 reserved: 31;
-} __attribute__ ((packed));
+} __packed;
#define HECI_EOP_STATUS_SUCCESS 0x0
#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
@@ -312,7 +314,7 @@ struct icc_clock_enables_msg {
struct me_global_reset {
u8 request_origin;
u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
typedef enum {
ME_NORMAL_BIOS_PATH,
@@ -373,21 +375,21 @@ typedef struct {
u32 mbp_size : 8;
u32 num_entries : 8;
u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
typedef struct {
u32 app_id : 8;
u32 item_id : 8;
u32 length : 8;
u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
+} __packed mbp_item_header;
typedef struct {
u32 major_version : 16;
u32 minor_version : 16;
u32 hotfix_version : 16;
u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
typedef struct {
u32 full_net : 1;
@@ -409,13 +411,13 @@ typedef struct {
u32 reserved_4 : 1;
u32 wlan : 1;
u32 reserved_5 : 8;
-} __attribute__ ((packed)) mbp_mefwcaps;
+} __packed mbp_mefwcaps;
typedef struct {
u16 device_id;
u16 fuse_test_flags;
u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
+} __packed mbp_rom_bist_data;
typedef struct {
u32 key[8];
@@ -433,7 +435,7 @@ typedef struct {
u32 image_type: 4;
u32 brand: 4;
u32 rsvd1: 16;
-} __attribute__ ((packed)) mbp_me_firmware_type;
+} __packed mbp_me_firmware_type;
typedef struct {
mbp_me_firmware_type rule_data;
@@ -443,7 +445,7 @@ typedef struct {
typedef struct {
u16 icc_start_address;
u16 mask;
-} __attribute__ ((packed)) icc_address_mask;
+} __packed icc_address_mask;
typedef struct {
u8 num_icc_profiles;
@@ -452,7 +454,7 @@ typedef struct {
u8 reserved;
u32 icc_reg_bundles;
icc_address_mask icc_address_mask[0];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
typedef struct {
u16 lock_state : 1;
@@ -461,24 +463,24 @@ typedef struct {
u16 flash_wear_out : 1;
u16 flash_variable_security : 1;
u16 reserved : 11;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
typedef struct {
u8 state;
u8 last_theft_trigger;
tdt_state_flag flags;
-} __attribute__ ((packed)) mbp_at_state;
+} __packed mbp_at_state;
typedef struct {
u32 wake_event_mrst_time_ms;
u32 mrst_pltrst_time_ms;
u32 pltrst_cpurst_time_ms;
-} __attribute__ ((packed)) mbp_plat_time;
+} __packed mbp_plat_time;
typedef struct {
u32 device_type : 2;
u32 reserved : 30;
-} __attribute__ ((packed)) mbp_nfc_data;
+} __packed mbp_nfc_data;
typedef struct {
mbp_fw_version_name *fw_version_name;
@@ -498,6 +500,6 @@ struct me_fwcaps {
u8 length;
mbp_mefwcaps caps_sku;
u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index 50936cf..2e7baa9 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -124,7 +124,7 @@ typedef struct {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h
index 7ab5faf..25c8987 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.h
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.h
@@ -18,7 +18,7 @@
#include <stdint.h>
-
+#include <compiler.h>
/* the 16 bit control structure for ricoh cardbus bridge */
typedef struct pc16reg {
@@ -87,4 +87,4 @@ typedef struct pc16reg {
u8 resv8;
u8 resv9;
u8 smpga0;
-} __attribute__ ((packed)) pc16reg_t;
+} __packed pc16reg_t;
diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h
index 9e543d4..e4166dd 100644
--- a/src/southbridge/via/vt8237r/nvs.h
+++ b/src/southbridge/via/vt8237r/nvs.h
@@ -38,4 +38,4 @@ typedef struct {
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index d745b49..7353839 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -16,6 +16,8 @@
#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
+#include <compiler.h>
+
/* Static resources for the VT8237R southbridge */
#define VT8237R_APIC_ID 0x2
@@ -121,7 +123,7 @@ struct vt8237_network_rom {
u8 cfg_c;
u8 cfg_d;
u8 checksum;
-} __attribute__ ((packed));
+} __packed;
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index 10f7386..82cd409 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -16,6 +16,8 @@
#ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H
#define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H
+#include <compiler.h>
+
#define BOOT_REASON_OTHER 0
#define BOOT_REASON_S3DIAG 9
@@ -57,7 +59,7 @@ typedef struct {
u32 ramoops_base; // dbe ramoops base address
u32 ramoops_len; // dc2 ramoops length
u8 pad[314]; // dc6-eff
-} __attribute__((packed)) chromeos_acpi_t;
+} __packed chromeos_acpi_t;
extern chromeos_acpi_t *vboot_data;
void chromeos_init_vboot(chromeos_acpi_t *chromeos);
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index 266ce4f..b3e9d18 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -17,6 +17,7 @@
#include <commonlib/region.h>
#include <stdint.h>
+#include <compiler.h>
#include <vboot_api.h>
#include <vboot_struct.h>
@@ -41,7 +42,7 @@ struct vboot_handoff {
VbInitParams init_params;
uint32_t selected_firmware;
char shared_data[VB_SHARED_DATA_MIN_SIZE];
-} __attribute__((packed));
+} __packed;
/*
* vboot_get_handoff_info returns pointer to the vboot_handoff structure if
diff --git a/src/vendorcode/google/chromeos/vpd_tables.h b/src/vendorcode/google/chromeos/vpd_tables.h
index d58b5e8..c866ec8 100644
--- a/src/vendorcode/google/chromeos/vpd_tables.h
+++ b/src/vendorcode/google/chromeos/vpd_tables.h
@@ -10,6 +10,7 @@
#define __LIB_VPD_TABLES_H__
#include <inttypes.h>
+#include <compiler.h>
#define VPD_ENTRY_MAGIC "_SM_"
#define VPD_INFO_MAGIC \
@@ -32,7 +33,7 @@ struct google_vpd_info {
uint8_t magic[12];
} header;
uint32_t size;
-} __attribute__((packed));
+} __packed;
/* Entry */
struct vpd_entry {
@@ -50,14 +51,14 @@ struct vpd_entry {
uint32_t table_address;
uint16_t table_entry_count;
uint8_t bcd_revision;
-} __attribute__ ((packed));
+} __packed;
/* Header */
struct vpd_header {
uint8_t type;
uint8_t length;
uint16_t handle;
-} __attribute__ ((packed));
+} __packed;
/* Type 0 - firmware information */
struct vpd_table_firmware {
@@ -72,7 +73,7 @@ struct vpd_table_firmware {
uint8_t minor_ver; /* v2.4+ */
uint8_t ec_major_ver; /* v2.4+ */
uint8_t ec_minor_ver; /* v2.4+ */
-} __attribute__ ((packed));
+} __packed;
/* Type 1 - system information */
struct vpd_table_system {
@@ -84,12 +85,12 @@ struct vpd_table_system {
uint8_t wakeup_type;
uint8_t sku_number; /* v2.4+ */
uint8_t family; /* v2.4+ */
-} __attribute__ ((packed));
+} __packed;
/* Type 127 - end of table */
struct vpd_table_eot {
struct vpd_header header;
-} __attribute__ ((packed));
+} __packed;
/* Type 241 - binary blob pointer */
struct vpd_table_binary_blob_pointer {
@@ -104,7 +105,7 @@ struct vpd_table_binary_blob_pointer {
uint8_t uuid[16];
uint32_t offset;
uint32_t size;
-} __attribute__ ((packed));
+} __packed;
/* The length and number of strings defined here is not a limitation of VPD.
* These numbers were deemed good enough during development. */
diff --git a/util/cbfstool/compiler.h b/util/cbfstool/compiler.h
new file mode 100644
index 0000000..293d659
--- /dev/null
+++ b/util/cbfstool/compiler.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#define __packed __attribute__((packed))
+#define __aligned(x) __attribute__((aligned(x)))
+#define __always_unused __attribute((unused))
+
+#endif
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