[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Wed Jul 27 21:14:41 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15849
-gerrit
commit 06999a8edef339ddc5474b253596494afcdbc723
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Jul 24 08:26:06 2016 -0700
drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
Display the MTRR values in the following locations:
* Before the call to FspMemoryInit to document coreboot settings
* After the call to FspMemoryInit
* After MTRR setup in postcar to document new coreboot settings
* After the call to FspSiliconInit
* After the call to FspNotify
TEST=Build and run on Galileo Gen2
Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/arch/x86/exit_car.S | 3 +++
src/drivers/intel/fsp2_0/include/fsp/debug.h | 36 ++++++++++++++++++++++++++++
src/drivers/intel/fsp2_0/include/fsp/util.h | 1 +
src/drivers/intel/fsp2_0/memory_init.c | 2 ++
src/drivers/intel/fsp2_0/notify.c | 1 +
src/drivers/intel/fsp2_0/silicon_init.c | 1 +
src/soc/intel/common/Makefile.inc | 4 ++++
7 files changed, 48 insertions(+)
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index a51d662..90715e4 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -108,6 +108,9 @@ _start:
wrmsr
#endif /* CONFIG_SOC_SETS_MSRS */
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
/* Load and run ramstage. */
call copy_and_run
/* Should never return. */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h
new file mode 100644
index 0000000..7dbd945
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_DEBUG_H_
+#define _FSP2_0_DEBUG_H_
+
+#include <fsp/util.h>
+#include <soc/intel/common/util.h>
+
+static inline __attribute__((always_inline)) void fsp_debug_memory_init(void)
+{
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+}
+
+static inline __attribute__((always_inline)) void fsp_debug_silicon_init(void)
+{
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+}
+
+static inline __attribute__((always_inline)) void fsp_debug_notify(void)
+{
+ /* Display the MTRRs */
+ soc_display_mtrrs();
+}
+
+#endif /* _FSP2_0_DEBUG_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index 01186f7..cc70cc1 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -16,6 +16,7 @@
#include <boot/coreboot_tables.h>
#include <commonlib/region.h>
#include <fsp/api.h>
+#include <fsp/debug.h>
#include <fsp/info_header.h>
#include <memrange.h>
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 5b93a30..ecd8761 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -63,6 +63,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake,
struct range_entry fsp_mem;
struct romstage_handoff *handoff;
+ fsp_debug_memory_init();
fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
/* initialize cbmem by adding FSP reserved memory first thing */
@@ -290,6 +291,7 @@ enum fsp_status fsp_memory_init(bool s3wake)
struct memranges memmap;
struct range_entry freeranges[2];
+ soc_display_mtrrs();
if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
return FSP_NOT_FOUND;
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 4e7e9c5..b83e982 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -55,6 +55,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase)
timestamp_add_now(TS_FSP_AFTER_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
+ fsp_debug_notify();
return ret;
}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index c069ff1..0da658e 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -56,6 +56,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
/* Handle any resets requested by FSPS. */
fsp_handle_reset(status);
+ fsp_debug_silicon_init();
return status;
}
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index e9ad508..81ef660 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
+bootblock-y += util.c
+
verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
@@ -9,6 +11,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
+postcar-y += util.c
+
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
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