[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/x4x: Fix CAS latency detection and max memory detection

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b
Author: Damien Zammit <damien at zamaudio.com>
Date:   Sun Jul 24 03:28:42 2016 +1000

    nb/intel/x4x: Fix CAS latency detection and max memory detection
    
    Now hardcode maximum memory frequency capability to 800MHz, as
    all chipsets in x4x family support PC2-6400 according to the datasheet.
    CAS latency detection also relies on this, and has been cleaned up.
    
    Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
    so disable this combination for now, and reduce to 667MHz instead.
    Still don't know why this is the case, but FSB1333/667 works.
    
    These changes should now allow existing configurations to continue working,
    while providing support for previously unworking configurations, due to
    previous buggy CAS latency detection code.
    
    TESTED: on GA-G41M-ES2L
    CPU: E5200 @ 2.50GHz (FSB 800MHz)
    
    2x 1GB 667MHz hynix	worked @ 667
    1x 2GB 800Mhz ARAM	worked @ 800
    1x 1GB 667Mhz StarRam	worked @ 667
    2x 2GB 800Mhz (generic)	worked @ 800
    
    Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
    Reviewed-on: https://review.coreboot.org/15818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>


See https://review.coreboot.org/15818 for details.

-gerrit