[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/bolt: remove unobtainable mainboard
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Jul 27 06:49:39 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15901
-gerrit
commit 401c0d7ecbf2c293d621905c006c0c157255ec6f
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Jul 26 11:48:06 2016 -0500
mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/bolt/Kconfig | 58 -------
src/mainboard/google/bolt/Kconfig.name | 2 -
src/mainboard/google/bolt/Makefile.inc | 41 -----
src/mainboard/google/bolt/acpi/chromeos.asl | 19 ---
src/mainboard/google/bolt/acpi/ec.asl | 20 ---
.../google/bolt/acpi/haswell_pci_irqs.asl | 82 ----------
src/mainboard/google/bolt/acpi/mainboard.asl | 105 -------------
src/mainboard/google/bolt/acpi/platform.asl | 82 ----------
src/mainboard/google/bolt/acpi/superio.asl | 25 ---
src/mainboard/google/bolt/acpi/thermal.asl | 168 ---------------------
src/mainboard/google/bolt/acpi_tables.c | 90 -----------
src/mainboard/google/bolt/board_info.txt | 5 -
src/mainboard/google/bolt/chromeos.c | 91 -----------
src/mainboard/google/bolt/chromeos.fmd | 38 -----
src/mainboard/google/bolt/cmos.layout | 110 --------------
src/mainboard/google/bolt/devicetree.cb | 116 --------------
src/mainboard/google/bolt/dsdt.asl | 60 --------
src/mainboard/google/bolt/ec.c | 47 ------
src/mainboard/google/bolt/ec.h | 59 --------
.../google/bolt/elpida_4Gb_1600_x16.spd.hex | 32 ----
src/mainboard/google/bolt/fadt.c | 152 -------------------
src/mainboard/google/bolt/gpio.h | 120 ---------------
src/mainboard/google/bolt/hda_verb.c | 79 ----------
src/mainboard/google/bolt/mainboard.c | 95 ------------
.../google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex | 32 ----
src/mainboard/google/bolt/onboard.h | 36 -----
src/mainboard/google/bolt/romstage.c | 162 --------------------
.../google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex | 32 ----
src/mainboard/google/bolt/smihandler.c | 155 -------------------
src/mainboard/google/bolt/thermal.h | 39 -----
30 files changed, 2152 deletions(-)
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig
deleted file mode 100644
index 3f34c9d..0000000
--- a/src/mainboard/google/bolt/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-if BOARD_GOOGLE_BOLT
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_HASWELL
- select NORTHBRIDGE_INTEL_HASWELL
- select SOUTHBRIDGE_INTEL_LYNXPOINT
- select INTEL_LYNXPOINT_LP
- select BOARD_ROMSIZE_KB_8192
- select EC_GOOGLE_CHROMEEC
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_RESUME
- select MMCONF_SUPPORT
- select HAVE_SMI_HANDLER
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select INTEL_INT15
-
-config CHROMEOS
- select CHROMEOS_VBNV_CMOS
- select LID_SWITCH
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/bolt
-
-config MAINBOARD_PART_NUMBER
- string
- default "Bolt"
-
-config MMCONF_BASE_ADDRESS
- hex
- default 0xf0000000
-
-config MAX_CPUS
- int
- default 8
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0166.rom"
-
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "X86 BOLT TEST 1863"
-endif
diff --git a/src/mainboard/google/bolt/Kconfig.name b/src/mainboard/google/bolt/Kconfig.name
deleted file mode 100644
index 4794eca..0000000
--- a/src/mainboard/google/bolt/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_BOLT
- bool "Bolt"
diff --git a/src/mainboard/google/bolt/Makefile.inc b/src/mainboard/google/bolt/Makefile.inc
deleted file mode 100644
index 3397af0..0000000
--- a/src/mainboard/google/bolt/Makefile.inc
+++ /dev/null
@@ -1,41 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = micron_4Gb_1600_1.35v_x16
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd rom data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/bolt/acpi/chromeos.asl b/src/mainboard/google/bolt/acpi/chromeos.asl
deleted file mode 100644
index ac4e843..0000000
--- a/src/mainboard/google/bolt/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
- Package () { 0x0003, 1, 16, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/bolt/acpi/ec.asl b/src/mainboard/google/bolt/acpi/ec.asl
deleted file mode 100644
index b9a6f5d..0000000
--- a/src/mainboard/google/bolt/acpi/ec.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/bolt/ec.h>
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/bolt/acpi/haswell_pci_irqs.asl b/src/mainboard/google/bolt/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index bc6053c..0000000
--- a/src/mainboard/google/bolt/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 18 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 21 },
- Package() { 0x001fffff, 1, 0, 18 },
- Package() { 0x001fffff, 2, 0, 17 },
- Package() { 0x001fffff, 3, 0, 16 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, 0, 20 },
- Package() { 0x0015ffff, 1, 0, 21 },
- Package() { 0x0015ffff, 2, 0, 21 },
- Package() { 0x0015ffff, 3, 0, 21 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, 0, 23 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/bolt/acpi/mainboard.asl b/src/mainboard/google/bolt/acpi/mainboard.asl
deleted file mode 100644
index af2503e..0000000
--- a/src/mainboard/google/bolt/acpi/mainboard.asl
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/bolt/onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-
- Device (TPAD)
- {
- Name (_ADR, 0x0)
- Name (_UID, 1)
-
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
-
- Name (_CRS, ResourceTemplate()
- {
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
-
- VendorShort (ADDR)
- {
- BOARD_TRACKPAD_I2C_ADDR
- }
- })
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
-
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
- }
- }
- }
-
- Device (TSCR)
- {
- Name (_ADR, 0x0)
- Name (_UID, 2)
-
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
-
- Name (_CRS, ResourceTemplate()
- {
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TOUCHSCREEN_IRQ
- }
-
- VendorShort (ADDR)
- {
- BOARD_TOUCHSCREEN_I2C_ADDR
- }
- })
-
- Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
-
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
- }
- }
- }
-}
diff --git a/src/mainboard/google/bolt/acpi/platform.asl b/src/mainboard/google/bolt/acpi/platform.asl
deleted file mode 100644
index 1bd054d..0000000
--- a/src/mainboard/google/bolt/acpi/platform.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, // APM command
- APMS, 8 // APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
- DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Update AC status */
- Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
- if (LNotEqual (Local0, \PWRS)) {
- Store (Local0, \PWRS)
- Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
- }
-
- /* Update LID status */
- Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
- if (LNotEqual (Local0, \LIDS)) {
- Store (Local0, \LIDS)
- Notify (\_SB.LID0, 0x80)
- }
-
- Return(Package(){0,0})
-}
diff --git a/src/mainboard/google/bolt/acpi/superio.asl b/src/mainboard/google/bolt/acpi/superio.asl
deleted file mode 100644
index b5d7c6e..0000000
--- a/src/mainboard/google/bolt/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/bolt/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/bolt/acpi/thermal.asl b/src/mainboard/google/bolt/acpi/thermal.asl
deleted file mode 100644
index 0aae633..0000000
--- a/src/mainboard/google/bolt/acpi/thermal.asl
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
- ThermalZone (THRM)
- {
- Name (_TC1, 0x02)
- Name (_TC2, 0x05)
-
- // Thermal zone polling frequency: 10 seconds
- Name (_TZP, 100)
-
- // Thermal sampling period for passive cooling: 2 seconds
- Name (_TSP, 20)
-
- // Convert from Degrees C to 1/10 Kelvin for ACPI
- Method (CTOK, 1) {
- // 10th of Degrees C
- Multiply (Arg0, 10, Local0)
-
- // Convert to Kelvin
- Add (Local0, 2732, Local0)
-
- Return (Local0)
- }
-
- // Threshold for OS to shutdown
- Method (_CRT, 0, Serialized)
- {
- Return (CTOK (\TCRT))
- }
-
- // Threshold for passive cooling
- Method (_PSV, 0, Serialized)
- {
- Return (CTOK (\TPSV))
- }
-
- // Processors used for passive cooling
- Method (_PSL, 0, Serialized)
- {
- Return (\PPKG ())
- }
-
- Method (_TMP, 0, Serialized)
- {
- // Get Temperature from TIN# set in NVS
- Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
-
- // Check for sensor not calibrated
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not present
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not powered
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
- Return (CTOK(0))
- }
-
- // Check for sensor bad reading
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
- Return (CTOK(0))
- }
-
- // Adjust by offset to get Kelvin
- Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
-
- // Convert to 1/10 Kelvin
- Multiply (Local0, 10, Local0)
- Return (Local0)
- }
-
- /* CTDP Down */
- Method (_AC0) {
- If (LLessEqual (\FLVL, 0)) {
- Return (CTOK (\F0OF))
- } Else {
- Return (CTOK (\F0ON))
- }
- }
-
- /* CTDP Nominal */
- Method (_AC1) {
- If (LLessEqual (\FLVL, 1)) {
- Return (CTOK (\F1OF))
- } Else {
- Return (CTOK (\F1ON))
- }
- }
-
- Name (_AL0, Package () { TDP0 })
- Name (_AL1, Package () { TDP1 })
-
- PowerResource (TNP0, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 0)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (0, \FLVL)
- \_SB.PCI0.MCHC.STND ()
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
- \_SB.PCI0.MCHC.STDN ()
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- PowerResource (TNP1, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 1)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- Device (TDP0)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 0)
- Name (_PR0, Package () { TNP0 })
- }
-
- Device (TDP1)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 1)
- Name (_PR0, Package () { TNP1 })
- }
- }
-}
diff --git a/src/mainboard/google/bolt/acpi_tables.c b/src/mainboard/google/bolt/acpi_tables.c
deleted file mode 100644
index 68ca066..0000000
--- a/src/mainboard/google/bolt/acpi_tables.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include "thermal.h"
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
- gnvs->tmps = CTDP_SENSOR_ID;
-
- gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
- gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON;
-
- gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF;
- gnvs->f0on = CTDP_DOWN_THRESHOLD_ON;
-
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
- gnvs->flvl = 1;
-}
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- /* Enable USB ports in S3 */
- gnvs->s3u0 = 1;
- gnvs->s3u1 = 1;
-
- /* Disable USB ports in S5 */
- gnvs->s5u0 = 0;
- gnvs->s5u1 = 0;
-
- /* TPM Present */
- gnvs->tpmp = 1;
-
-
-#if CONFIG_CHROMEOS
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
- acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
diff --git a/src/mainboard/google/bolt/board_info.txt b/src/mainboard/google/bolt/board_info.txt
deleted file mode 100644
index eca915f..0000000
--- a/src/mainboard/google/bolt/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: eval
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c
deleted file mode 100644
index 4bf2a78..0000000
--- a/src/mainboard/google/bolt/chromeos.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <bootmode.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
-
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include "ec.h"
-#include <ec/google/chromeec/ec.h>
-#endif
-
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 16
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_lid_switch(void)
-{
-#if CONFIG_EC_GOOGLE_CHROMEEC
- u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
-
- return !!(ec_switches & EC_SWITCH_LID_OPEN);
-#else
- return 0;
-#endif
-}
-
-/* The dev-switch is virtual */
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-/* There are actually two recovery switches. One is the magic keyboard chord,
- * the other is driven by Servo. */
-int get_recovery_mode_switch(void)
-{
-#if CONFIG_EC_GOOGLE_CHROMEEC
- u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
- u32 ec_events;
-
- /* If a switch is set, we don't need to look at events. */
- if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
- return 1;
-
- /* Else check if the EC has posted the keyboard recovery event. */
- ec_events = google_chromeec_get_events_b();
-
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-#else
- return 0;
-#endif
-}
-
-int get_write_protect_state(void)
-{
- return get_gpio(CROS_WP_GPIO);
-}
diff --git a/src/mainboard/google/bolt/chromeos.fmd b/src/mainboard/google/bolt/chromeos.fmd
deleted file mode 100644
index 113fba6..0000000
--- a/src/mainboard/google/bolt/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH at 0xff800000 0x800000 {
- SI_ALL at 0x0 0x200000 {
- SI_DESC at 0x0 0x1000
- SI_ME at 0x1000 0x1ff000
- }
- SI_BIOS at 0x200000 0x600000 {
- RW_SECTION_A at 0x0 0xf0000 {
- VBLOCK_A at 0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0xdffc0
- RW_FWID_A at 0xeffc0 0x40
- }
- RW_SECTION_B at 0xf0000 0xf0000 {
- VBLOCK_B at 0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0xdffc0
- RW_FWID_B at 0xeffc0 0x40
- }
- RW_MRC_CACHE at 0x1e0000 0x10000
- RW_ELOG at 0x1f0000 0x4000
- RW_SHARED at 0x1f4000 0x4000 {
- SHARED_DATA at 0x0 0x2000
- VBLOCK_DEV at 0x2000 0x2000
- }
- RW_VPD at 0x1f8000 0x2000
- RW_UNUSED at 0x1fa000 0x6000
- RW_LEGACY(CBFS)@0x200000 0x200000
- WP_RO at 0x400000 0x200000 {
- RO_VPD at 0x0 0x4000
- RO_UNUSED at 0x4000 0xc000
- RO_SECTION at 0x10000 0x1f0000 {
- FMAP at 0x0 0x800
- RO_FRID at 0x800 0x40
- RO_FRID_PAD at 0x840 0x7c0
- GBB at 0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x100000
- }
- }
- }
-}
diff --git a/src/mainboard/google/bolt/cmos.layout b/src/mainboard/google/bolt/cmos.layout
deleted file mode 100644
index 2a518e9..0000000
--- a/src/mainboard/google/bolt/cmos.layout
+++ /dev/null
@@ -1,110 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 r 0 reboot_bits
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416 128 r 0 vbnv
-#544 440 r 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb
deleted file mode 100644
index 1acd781..0000000
--- a/src/mainboard/google/bolt/devicetree.cb
+++ /dev/null
@@ -1,116 +0,0 @@
-chip northbridge/intel/haswell
- # IGD Displays
- register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
-
- # Enable eDP Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Disable DDI2 Hotplug
- register "gpu_dp_c_hotplug" = "0x00"
-
- # Enable DDI1 Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
-
- # Set backlight PWM values for eDP
- register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
-
- # Enable Panel and configure power delays
- register "gpu_panel_port_select" = "1" # eDP
- register "gpu_panel_power_cycle_delay" = "6" # 500ms
- register "gpu_panel_power_up_delay" = "2000" # 200ms
- register "gpu_panel_power_down_delay" = "500" # 50ms
- register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
- register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
-
- device cpu_cluster 0 on
- chip cpu/intel/haswell
- device lapic 0 on end
- # Magic APIC ID to locate this chip
- device lapic 0xACAC off end
-
- register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10)
-
- register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10)
- end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
-
- chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
- register "sata_port_map" = "0x1"
-
- register "sio_acpi_mode" = "0"
- register "sio_i2c0_voltage" = "0" # 3.3V
- register "sio_i2c1_voltage" = "0" # 3.3V
-
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 on end # SMBus
- device pci 1f.6 on end # Thermal
- end
- end
-end
diff --git a/src/mainboard/google/bolt/dsdt.asl b/src/mainboard/google/bolt/dsdt.asl
deleted file mode 100644
index 9e5a114..0000000
--- a/src/mainboard/google/bolt/dsdt.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define ENABLE_TPM
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
-
- // global NVS and variables
- #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-
- // General Purpose Events
- //#include "acpi/gpe.asl"
-
- // CPU
- #include <cpu/intel/haswell/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <northbridge/intel/haswell/acpi/haswell.asl>
- #include <southbridge/intel/lynxpoint/acpi/pch.asl>
-
- #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
- }
- }
-
- // Thermal handler
- #include "acpi/thermal.asl"
-
- // Chrome OS specific
- #include "acpi/chromeos.asl"
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- // Chipset specific sleep states
- #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c
deleted file mode 100644
index c011f33..0000000
--- a/src/mainboard/google/bolt/ec.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <types.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- printk(BIOS_DEBUG, "mainboard_ec_init\n");
- post_code(0xf0);
-
- /* Restore SCI event mask on resume. */
- if (acpi_is_wakeup_s3()) {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S3_WAKE_EVENTS);
-
- /* Disable SMI and wake events */
- google_chromeec_set_smi_mask(0);
-
- /* Clear pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- } else {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S5_WAKE_EVENTS);
- }
-
- /* Clear wake events, these are enabled on entry to sleep */
- google_chromeec_set_wake_mask(0);
-
- post_code(0xf1);
-}
diff --git a/src/mainboard/google/bolt/ec.h b/src/mainboard/google/bolt/ec.h
deleted file mode 100644
index c157351..0000000
--- a/src/mainboard/google/bolt/ec.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/google/chromeec/ec_commands.h>
-
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
-#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
-
-#ifndef __ACPI__
-extern void mainboard_ec_init(void);
-#endif
-
-#endif
diff --git a/src/mainboard/google/bolt/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/google/bolt/elpida_4Gb_1600_x16.spd.hex
deleted file mode 100644
index ef36c39..0000000
--- a/src/mainboard/google/bolt/elpida_4Gb_1600_x16.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-92 10 0b 03 04 19 02 02
-03 52 01 08 0a 00 fe 00
-69 78 69 3c 69 11 18 81
-20 08 3c 3c 01 40 83 81
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 0f 11 42 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 02 fe 00
-11 52 00 00 00 07 7f 37
-45 42 4a 32 30 55 47 36
-45 42 55 30 2d 47 4e 2d
-46 20 30 20 02 fe 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/bolt/fadt.c b/src/mainboard/google/bolt/fadt.c
deleted file mode 100644
index 2452ac2..0000000
--- a/src/mainboard/google/bolt/fadt.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
- u16 pmbase = get_pmbase();
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = PM_MOBILE;
-
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x80;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 32;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 87;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 0;
- fadt->x_gpe0_blk.bit_width = 0;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/google/bolt/gpio.h b/src/mainboard/google/bolt/gpio.h
deleted file mode 100644
index a7c2453..0000000
--- a/src/mainboard/google/bolt/gpio.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef BOLT_GPIO_H
-#define BOLT_GPIO_H
-
-struct pch_lp_gpio_map;
-
-const struct pch_lp_gpio_map mainboard_gpio_map[] = {
- LP_GPIO_UNUSED, /* 0: UNUSED */
- LP_GPIO_UNUSED, /* 1: UNUSED */
- LP_GPIO_UNUSED, /* 2: UNUSED */
- LP_GPIO_UNUSED, /* 3: UNUSED */
- LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
- LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
- LP_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
- LP_GPIO_UNUSED, /* 9: UNUSED */
- LP_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
- LP_GPIO_UNUSED, /* 11: UNUSED */
- LP_GPIO_UNUSED, /* 12: UNUSED */
- LP_GPIO_INPUT_INVERT, /* 13: TRACKPAD_INT_L (WAKE) */
- LP_GPIO_INPUT_INVERT, /* 14: TOUCH_INT_L (WAKE) */
- LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- LP_GPIO_INPUT, /* 16: PCH_WP */
- LP_GPIO_UNUSED, /* 17: UNUSED */
- LP_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */
- LP_GPIO_UNUSED, /* 19: UNUSED */
- LP_GPIO_UNUSED, /* 20: UNUSED */
- LP_GPIO_UNUSED, /* 21: UNUSED */
- LP_GPIO_UNUSED, /* 22: UNUSED */
- LP_GPIO_UNUSED, /* 23: UNUSED */
- LP_GPIO_UNUSED, /* 24: UNUSED */
- LP_GPIO_INPUT, /* 25: EC_IN_RW */
- LP_GPIO_UNUSED, /* 26: UNUSED */
- LP_GPIO_UNUSED, /* 27: UNUSED */
- LP_GPIO_UNUSED, /* 28: UNUSED */
- LP_GPIO_INPUT, /* 29: NATIVE: WLAN_OFF_L */
- LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
- LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- LP_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
- LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- LP_GPIO_UNUSED, /* 37: UNUSED */
- LP_GPIO_UNUSED, /* 38: UNUSED */
- LP_GPIO_UNUSED, /* 39: UNUSED */
- LP_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
- LP_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
- LP_GPIO_UNUSED, /* 42: UNUSED */
- LP_GPIO_UNUSED, /* 43: UNUSED */
- LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
- LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
- LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
- LP_GPIO_UNUSED, /* 47: UNUSED */
- LP_GPIO_OUT_HIGH, /* 48: TPM_LP_EN_L */
- LP_GPIO_OUT_HIGH, /* 49: HDMI_CEC */
- LP_GPIO_UNUSED, /* 50: UNUSED */
- LP_GPIO_INPUT, /* 51: ALS_INT_L */
- LP_GPIO_INPUT, /* 52: SIM_DET */
- LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_L_R (PIRQV) */
- LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_R (PIRQW) */
- LP_GPIO_UNUSED, /* 55: UNUSED */
- LP_GPIO_UNUSED, /* 56: UNUSED */
- LP_GPIO_OUT_HIGH, /* 57: PP3300_AUTOBAHN_EN */
- LP_GPIO_UNUSED, /* 58: UNUSED */
- LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- LP_GPIO_UNUSED, /* 60: UNUSED */
- LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
- LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
- LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- LP_GPIO_UNUSED, /* 64: UNUSED */
- LP_GPIO_UNUSED, /* 65: UNUSED */
- LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 67: UNUSED */
- LP_GPIO_UNUSED, /* 68: UNUSED */
- LP_GPIO_UNUSED, /* 69: UNUSED */
- LP_GPIO_UNUSED, /* 70: UNUSED */
- LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- LP_GPIO_UNUSED, /* 72: UNUSED */
- LP_GPIO_UNUSED, /* 73: UNUSED */
- LP_GPIO_UNUSED, /* 74: UNUSED */
- LP_GPIO_UNUSED, /* 75: UNUSED */
- LP_GPIO_UNUSED, /* 76: UNUSED */
- LP_GPIO_UNUSED, /* 77: UNUSED */
- LP_GPIO_UNUSED, /* 78: UNUSED */
- LP_GPIO_UNUSED, /* 79: UNUSED */
- LP_GPIO_UNUSED, /* 80: UNUSED */
- LP_GPIO_NATIVE, /* 81: NATIVE: PCH_HDA_SPKR */
- LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- LP_GPIO_UNUSED, /* 83: UNUSED */
- LP_GPIO_UNUSED, /* 84: UNUSED */
- LP_GPIO_UNUSED, /* 85: UNUSED */
- LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 87: UNUSED */
- LP_GPIO_UNUSED, /* 88: UNUSED */
- LP_GPIO_UNUSED, /* 89: UNUSED */
- LP_GPIO_UNUSED, /* 90: UNUSED */
- LP_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */
- LP_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */
- LP_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */
- LP_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */
- LP_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/bolt/hda_verb.c b/src/mainboard/google/bolt/hda_verb.c
deleted file mode 100644
index bf1129e..0000000
--- a/src/mainboard/google/bolt/hda_verb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
- 0x10ec0283, // Subsystem ID
- 0x0000000b, // Number of jacks (NID entries)
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
- AZALIA_SUBVENDOR(0x0, 0x10ec0283),
-
- /* Pin Widget Verb Table */
-
- /* Pin Complex (NID 0x12) DMIC - interior mobile lid */
- AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010),
-
- /* Pin Complex (NID 0x14) SPKR-OUT PORTD */
- // group 1, front left/right
- // no connector, no jack detect
- // speaker out, analog
- // fixed function, internal
- AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
-
- /* Pin Complex (NID 0x17) */
- AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
-
- /* Pin Complex (NID 0x18) MIC1 PORTB */
- // group 1, cap 1
- // black, jack detect
- // mic in, analog
- // connector, left panel
- AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011),
-
- /* Pin Complex (NID 0x19) MIC2 PORTF */
- AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
-
- /* Pin Complex (NID 0x1A) LINE1 PORTC */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
-
- /* Pin Complex (NID 0x1B) LINE2 PORTE */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
-
- /* Pin Complex (NID 0x1d) PCBeep */
- // eapd low on ex-amp, laptop, custom enable
- // mute spkr on hpout
- // pcbeep en able, checksum
- // no physical, internal
- AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
-
- /* Pin Complex (NID 0x1E) SPDIF-OUT */
- AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
-
- /* Pin Complex (NID 0x21) HPOUT PORT-I */
- // group1,
- // black, jack detect
- // HPOut, 1/8 stereo
- // connector, left panel
- AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
-
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c
deleted file mode 100644
index b9ce50e..0000000
--- a/src/mainboard/google/bolt/mainboard.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include "ec.h"
-#include "onboard.h"
-
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-
-
-static void mainboard_init(device_t dev)
-{
- mainboard_ec_init();
-}
-
-static int mainboard_smbios_data(device_t dev, int *handle,
- unsigned long *current)
-{
- int len = 0;
-
- len += smbios_write_type41(
- current, handle,
- BOARD_LIGHTSENSOR_NAME, /* name */
- BOARD_LIGHTSENSOR_IRQ, /* instance */
- BOARD_LIGHTSENSOR_I2C_BUS, /* segment */
- BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TRACKPAD_NAME, /* name */
- BOARD_TRACKPAD_IRQ, /* instance */
- BOARD_TRACKPAD_I2C_BUS, /* segment */
- BOARD_TRACKPAD_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TOUCHSCREEN_NAME, /* name */
- BOARD_TOUCHSCREEN_IRQ, /* instance */
- BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
- BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- return len;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- dev->ops->get_smbios_data = mainboard_smbios_data;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex
deleted file mode 100644
index 7ed2663..0000000
--- a/src/mainboard/google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-92 11 0b 03 04 19 02 02
-03 11 01 08 0a 00 fe 00
-69 78 69 3c 69 11 18 81
-20 08 3c 3c 01 40 83 05
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 0f 01 02 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 80 2c 00
-00 00 00 00 00 00 ad 75
-34 4b 54 46 32 35 36 36
-34 48 5a 2d 31 47 36 45
-31 20 45 31 80 2c 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
-ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/bolt/onboard.h b/src/mainboard/google/bolt/onboard.h
deleted file mode 100644
index c7e051c..0000000
--- a/src/mainboard/google/bolt/onboard.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_LIGHTSENSOR_NAME "lightsensor"
-#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */
-#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */
-#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44
-
-#define BOARD_TRACKPAD_NAME "trackpad"
-#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
-#define BOARD_TRACKPAD_WAKE_GPIO 13 /* GPIO13 */
-#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR 0x67
-
-#define BOARD_TOUCHSCREEN_NAME "touchscreen"
-#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
-#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */
-#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
-#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
-
-#endif
diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c
deleted file mode 100644
index 817fce9..0000000
--- a/src/mainboard/google/bolt/romstage.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/raminit.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include "gpio.h"
-
-const struct rcba_config_instruction rcba_config[] = {
-
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP PCIE INTA -> PIRQA
- * D29IP_E1P EHCI INTA -> PIRQD
- * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
- RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
- RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP)),
- RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
- RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
- RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
- RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
-
- /* Device interrupt route registers */
- RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
- RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
- RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
- RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
- RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
- RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
- RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
- RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
-
- /* Disable unused devices (board specific) */
- RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
-
- RCBA_END_CONFIG,
-};
-
-/* Copy SPD data for on-board memory */
-static void copy_spd(struct pei_data *peid)
-{
- char *spd_file;
- size_t spd_file_len;
- int spd_index = 0; /* No GPIO selection, force index 0 for now */
-
- printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len <
- ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < sizeof(peid->spd_data[0]))
- die("Missing SPD data.");
-
- memcpy(peid->spd_data[0],
- spd_file +
- spd_index * sizeof(peid->spd_data[0]),
- sizeof(peid->spd_data[0]));
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- struct pei_data pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = DEFAULT_PCIEXBAR,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
- .ec_present = 1,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
- .max_ddr3_freq = 1600,
- .usb2_ports = {
- /* Length, Enable, OCn#, Location */
- /* P0: HOST PORT - J7 */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- /* P1: HOST PORT - J6 */
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- /* P2: EMPTY */
- { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- /* P3: SD CARD */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX },
- /* P4: EMPTY */
- { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- /* P5: WWAN */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
- /* P6: CAMERA */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX },
- /* P7: BT */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
- },
- .usb3_ports = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1: HOST PORT - J7 */
- { 1, 1 }, /* P2: HOST PORT - J6 */
- { 0, USB_OC_PIN_SKIP }, /* P3: EMPTY */
- { 0, USB_OC_PIN_SKIP }, /* P4: EMPTY */
- },
- };
-
- struct romstage_params romstage_params = {
- .pei_data = &pei_data,
- .gpio_map = &mainboard_gpio_map,
- .rcba_config = &rcba_config[0],
- .bist = bist,
- .copy_spd = copy_spd,
- };
-
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(&romstage_params);
-}
diff --git a/src/mainboard/google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex
deleted file mode 100644
index 5beb5fc..0000000
--- a/src/mainboard/google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-92 11 0b 03 04 19 02 02
-03 11 01 08 0a 00 fe 00
-69 78 69 3c 69 11 18 81
-f0 0a 3c 3c 01 40 83 01
-00 80 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 0f 11 02 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 80 ce 01
-00 00 00 00 00 00 6a 04
-4d 34 37 31 42 35 36 37
-34 42 48 30 2d 59 4b 30
-20 20 00 00 80 ce 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c
deleted file mode 100644
index 91213eb..0000000
--- a/src/mainboard/google/bolt/smihandler.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <elog.h>
-
-/* Include EC functions */
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-static u8 mainboard_smi_ec(void)
-{
- u8 cmd = google_chromeec_get_event();
- u32 pm1_cnt;
-
-#if CONFIG_ELOG_GSMI
- /* Log this event */
- if (cmd)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
-#endif
-
- switch (cmd) {
- case EC_HOST_EVENT_LID_CLOSED:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
- /* Go to S5 */
- pm1_cnt = inl(get_pmbase() + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, get_pmbase() + PM1_CNT);
- break;
- }
-
- return cmd;
-}
-
-/* gpi_sts is GPIO 47:32 */
-void mainboard_smi_gpi(u32 gpi_sts)
-{
- if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
- /* Process all pending events */
- while (mainboard_smi_ec() != 0);
- }
-}
-
-static void bolt_wlan_off(void)
-{
- u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
- u32 gpio_conf;
-
- /* Make sure pin is owned by GPIO subsystem and not ACPI */
- gpio_conf = inl(gpio_base + GPIO_OWNER(0));
- gpio_conf |= GPIO_OWNER_GPIO << 29;
- outl(gpio_conf, gpio_base + GPIO_OWNER(0));
-
- /* Set GPIO29 config to only be reset on RSMRST */
- gpio_conf = inl(gpio_base + GPIO_RESET(0));
- gpio_conf |= GPIO_RESET_RSMRST << 29;
- outl(gpio_conf, gpio_base + GPIO_RESET(0));
-
- /* Set WLAN_OFF_L (GPIO29) as Output GPIO driven high */
- gpio_conf = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH;
- outl(gpio_conf, gpio_base + GPIO_CONFIG0(29));
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- /* Disable USB charging if required */
- switch (slp_typ) {
- case ACPI_S3:
- if (smm_get_gnvs()->s3u0 == 0)
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s3u1 == 0)
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- break;
- case ACPI_S5:
- if (smm_get_gnvs()->s5u0 == 0)
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s5u1 == 0)
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- break;
- }
-
- /* Set WLAN_OFF GPIO state */
- bolt_wlan_off();
-
- /* Disable SCI and SMI events */
- google_chromeec_set_smi_mask(0);
- google_chromeec_set_sci_mask(0);
-
- /* Clear pending events that may trigger immediate wake */
- while (google_chromeec_get_event() != 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
-}
-
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- case APM_CNT_ACPI_ENABLE:
- google_chromeec_set_smi_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- break;
- case APM_CNT_ACPI_DISABLE:
- google_chromeec_set_sci_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/google/bolt/thermal.h b/src/mainboard/google/bolt/thermal.h
deleted file mode 100644
index be700c7..0000000
--- a/src/mainboard/google/bolt/thermal.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-/* Config TDP Sensor ID */
-#define CTDP_SENSOR_ID 0 /* PECI */
-
-/* Config TDP Nominal */
-#define CTDP_NOMINAL_THRESHOLD_OFF 0
-#define CTDP_NOMINAL_THRESHOLD_ON 0
-
-/* Config TDP Down */
-#define CTDP_DOWN_THRESHOLD_OFF 75
-#define CTDP_DOWN_THRESHOLD_ON 85
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 99
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 100
-
-#endif
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