[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: Do not update MRC cache in recovery mode

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15828

-gerrit

commit 9c321db35c8de4f2453bc1ec0f27d3b1b7701225
Author: Furquan Shaikh <furquan at google.com>
Date:   Sun Jul 24 08:48:34 2016 -0700

    soc/intel/common: Do not update MRC cache in recovery mode
    
    If the system is in recovery, there is no need to update the MRC
    cache. Instead clear the MRC cache. This ensures that on next boot, the
    normal/developer mode boot will save its own MRC data.
    
    BUG=chrome-os-partner:55431
    
    Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/drivers/intel/fsp2_0/memory_init.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 8afa6d7..b439d90 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -57,6 +57,8 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
 			printk(BIOS_ERR, "Failed to stash MRC data\n");
 }
 
+#define MRC_DEAD_VERSION		(0xdeaddead)
+
 static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake,
 						uint32_t fsp_version)
 {
@@ -86,6 +88,9 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake,
 	/* Now that CBMEM is up, save the list so ramstage can use it */
 	fsp_save_hob_list(hob_list_ptr);
 
+	if (recovery_mode_enabled())
+		fsp_version = MRC_DEAD_VERSION;
+
 	save_memory_training_data(s3wake, fsp_version);
 
 	/* Create romstage handof information */