[coreboot-gerrit] Patch merged into coreboot/master: intel car: Use MTRR WRPROT type for XIP cache

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit dc4820baed8ac592a5583ebdd97c8ed892a5b0b6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jul 21 19:51:01 2016 +0300

    intel car: Use MTRR WRPROT type for XIP cache
    
    XIP cachelines contain the executable to run, we never want
    that to get modified. With the change such erronous writes
    are ignored and next cacheline miss will fetch from boot
    media (SPI / FWH flash).
    
    Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: https://review.coreboot.org/15778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15778 for details.

-gerrit