[coreboot-gerrit] Patch merged into coreboot/master: drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 27cd96a661558584977e8a491f5b433f31fa3a29
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Jul 21 11:16:39 2016 -0700

    drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M
    
    Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
    Quark executes romstage directly from the SPI flash part (in-place),
    but loads FSP-M into ESRAM.  This split occurs because ESRAM is too
    small to hold everything while debugging.
    
    Platforms executing FSP-M directly from the SPI flash need to select
    FSP_M_XIP.
    
    TEST=Build and run on Galileo Gen2.
    
    Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
    Reviewed-on: https://review.coreboot.org/15848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15848 for details.

-gerrit