[coreboot-gerrit] New patch to review for coreboot: cpu/x86: Support CPUs without rdmsr/wrmsr instructions

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15839

-gerrit

commit c932439aa7f2d1adc8bac3285df01e9f86dda890
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Sun Jul 24 08:03:37 2016 -0700

    cpu/x86: Support CPUs without rdmsr/wrmsr instructions
    
    Quark does not support the rdmsr and wrmsr instructions.  In this case
    use a SOC specific routine to support the setting of the MTRRs.  Migrate
    the code from FSP 1.1 to be x86 CPU common.
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/cpu/x86/Kconfig                             |  7 +++++++
 src/drivers/intel/fsp1_1/include/fsp/romstage.h |  7 -------
 src/include/cpu/x86/mtrr.h                      | 20 ++++++++++++++++++++
 src/soc/intel/common/Kconfig                    |  7 -------
 src/soc/intel/common/util.h                     |  7 -------
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 74d87e2..5f11bc7 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -153,3 +153,10 @@ config BOOT_MEDIA_SPI_BUS
 	depends on SPI_FLASH
 	help
 	 Most x86 systems which boot from SPI flash boot using bus 0.
+
+config SOC_SETS_MTRRS
+	bool
+	default n
+	help
+	  The SoC needs uses different access methods for reading and writing
+	  the MTRRs.  Use SoC specific routines to handle the MTRR access.
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index d07dc37..4683f5e 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -88,11 +88,4 @@ void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd);
 void soc_pre_ram_init(struct romstage_params *params);
 
-/*
- * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
- * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
- */
-asmlinkage void *soc_set_mtrrs(void *top_of_stack);
-asmlinkage void soc_enable_mtrrs(void);
-
 #endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index f33a4ac..4d28972 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -124,4 +124,24 @@ int get_free_var_mtrr(void);
 
 #define CACHE_ROM_BASE	(((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
 
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#include <cpu/x86/msr.h>
+
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+msr_t soc_mtrr_read(unsigned long index);
+void soc_mtrr_write(unsigned long index, msr_t msr);
+
+/*
+ * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
+ * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
+ */
+#include <arch/cpu.h>
+asmlinkage void *soc_set_mtrrs(void *top_of_stack);
+asmlinkage void soc_enable_mtrrs(void);
+#else
+#define soc_mtrr_read	rdmsr
+#define soc_mtrr_write	wrmsr
+#endif /* CONFIG_SOC_SETS_MTRRS */
+#endif
+
 #endif /* CPU_X86_MTRR_H */
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 776004b..a32252e 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -56,13 +56,6 @@ config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
 	  No default is set here as this is an SOC-specific value and must
 	  be provided by the SOC when it selects this driver.
 
-config SOC_SETS_MTRRS
-	bool
-	default n
-	help
-	  The SoC needs uses different access methods for reading and writing
-	  the MTRRs.  Use SoC specific routines to handle the MTRR access.
-
 config MMA
 	bool "enable MMA (Memory Margin Analysis) support"
 	default n
diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h
index 7d05e47..854f2b0 100644
--- a/src/soc/intel/common/util.h
+++ b/src/soc/intel/common/util.h
@@ -22,12 +22,5 @@
 
 asmlinkage void soc_display_mtrrs(void);
 uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
-#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
-msr_t soc_mtrr_read(unsigned long index);
-void soc_mtrr_write(unsigned long index, msr_t msr);
-#else
-#define soc_mtrr_read	rdmsr
-#define soc_mtrr_write	wrmsr
-#endif /* CONFIG_SOC_SETS_MTRRS */
 
 #endif /* _INTEL_COMMON_UTIL_H_ */