[coreboot-gerrit] Patch set updated for coreboot: meditek/mt8173: dsi: set mipi pin driving control on

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15807

-gerrit

commit a692b112e819dd31b565f8757867381fcf2cb623
Author: Jitao Shi <jitao.shi at mediatek.com>
Date:   Fri Jul 15 14:23:53 2016 +0800

    meditek/mt8173: dsi: set mipi pin driving control on
    
    We set this driving control to prevent signal attenuation caused by
    LVDS DRV termination.
    
    When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
    termination status is unknown (floating). This creates a chance that
    MIPI output would be influenced. The DSI's LP signal will be half
    voltage attenuation. There will be no display on panel.
    
    When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
    effective and termination is fixed OFF. The DSI won't be influenced.
    
    We only need to set this register once, so we set it here to prevent
    repeatedly setting in the kernel when the system goes to recovery mode.
    
    BUG=chrome-os-partner:55296
    BRANCH=none
    TEST=build pass elm and show ui
    
    Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
    Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
    Original-Signed-off-by: Jitao Shi <jitao.shi at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/360850
    Original-Commit-Ready: jitao shi <jitao.shi at mediatek.com>
    Original-Tested-by: jitao shi <jitao.shi at mediatek.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/mediatek/mt8173/dsi.c             | 19 +++++++++++++++++++
 src/soc/mediatek/mt8173/include/soc/dsi.h | 26 ++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index 1d19571..3500bf1 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -20,6 +20,7 @@
 #include <soc/i2c.h>
 #include <soc/gpio.h>
 #include <soc/dsi.h>
+#include <timer.h>
 
 static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
 				   const struct edid *edid)
@@ -298,3 +299,21 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes,
 
 	return 0;
 }
+
+void mtk_dsi_pin_drv_ctrl(void)
+{
+	struct stopwatch sw;
+
+	setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
+
+	stopwatch_init_usecs_expire(&sw, 1000);
+
+	do {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "enable lvdstx_power failed!!!\n");
+			return;
+		}
+	} while ((read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK) == 0);
+
+	clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
+}
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index 1abbd78..73f4425 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -263,7 +263,33 @@ enum {
 	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
 };
 
+/* LVDS_TX1_REG */
+struct lvds_tx1_regs {
+	u32 lvdstx1_ctl1;
+	u32 lvdstx1_ctl2;
+	u32 lvdstx1_ctl3;
+	u32 lvdstx1_ctl4;
+	u32 lvdstx1_ctl5;
+	u32 vopll_ctl1;
+	u32 vopll_ctl2;
+	u32 vopll_ctl3;
+};
+
+static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);
+
+/* LVDS_VOPLL_CTRL3 */
+enum {
+	RG_LVDSTX_21EDG = BIT(0),
+	RG_LVDSTX_21LEV = BIT(1),
+	RG_LVDSTX_51EDG = BIT(2),
+	RG_LVDSTX_51LEV = BIT(3),
+	RG_AD_LVDSTX_PWR_ACK = BIT(4),
+	RG_DA_LVDS_ISO_EN = BIT(8),
+	RG_DA_LVDSTX_PWR_ON = BIT(9)
+};
+
 int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes,
 		 const struct edid *edid);
+void mtk_dsi_pin_drv_ctrl(void);
 
 #endif