[coreboot-gerrit] Patch set updated for coreboot: bd82x6x: deduplicate the implementation of IOBP access functions [UNTESTED]
Felix Held (felix-coreboot@felixheld.de)
gerrit at coreboot.org
Sun Jul 24 16:53:27 CEST 2016
Felix Held (felix-coreboot at felixheld.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15827
-gerrit
commit 0eb8c509f83db5b42f4cced029f529815ad32aa2
Author: Felix Held <felix-coreboot at felixheld.de>
Date: Sun Jul 24 15:44:16 2016 +0200
bd82x6x: deduplicate the implementation of IOBP access functions [UNTESTED]
Change-Id: Iea2ae95ddd10ec69f1dbe69dde420bccc4de8a15
Signed-off-by: Felix Held <felix-coreboot at felixheld.de>
---
src/southbridge/intel/bd82x6x/early_pch.c | 154 ++++++++++++------------------
src/southbridge/intel/bd82x6x/pch.h | 2 +-
2 files changed, 60 insertions(+), 96 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 21a996d..957f937 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -30,42 +30,6 @@
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-static void
-wait_2338 (void)
-{
- while (read8 (DEFAULT_RCBA + 0x2338) & 1);
-}
-
-static u32
-read_2338 (u32 edx)
-{
- u32 ret;
-
- write32 (DEFAULT_RCBA + 0x2330, edx);
- write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
- & 0x1ff) | 0x600);
- wait_2338 ();
- ret = read32 (DEFAULT_RCBA + 0x2334);
- wait_2338 ();
- read8 (DEFAULT_RCBA + 0x2338);
- return ret;
-}
-
-static void
-write_2338 (u32 edx, u32 val)
-{
- read_2338 (edx);
- write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
- & 0x1ff) | 0x600);
- wait_2338 ();
-
- write32 (DEFAULT_RCBA + 0x2334, val);
- wait_2338 ();
- write16 (DEFAULT_RCBA + 0x2338,
- (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600);
- read8 (DEFAULT_RCBA + 0x2338);
-}
-
static void
init_dmi (void)
@@ -304,67 +268,67 @@ early_pch_init_native (void)
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
- write_2338 (0xea007f62, 0x00590133);
- write_2338 (0xec007f62, 0x00590133);
- write_2338 (0xec007f64, 0x59555588);
- write_2338 (0xea0040b9, 0x0001051c);
- write_2338 (0xeb0040a1, 0x800084ff);
- write_2338 (0xec0040a1, 0x800084ff);
- write_2338 (0xea004001, 0x00008400);
- write_2338 (0xeb004002, 0x40201758);
- write_2338 (0xec004002, 0x40201758);
- write_2338 (0xea004002, 0x00601758);
- write_2338 (0xea0040a1, 0x810084ff);
- write_2338 (0xeb0040b1, 0x0001c598);
- write_2338 (0xec0040b1, 0x0001c598);
- write_2338 (0xeb0040b6, 0x0001c598);
- write_2338 (0xea0000a9, 0x80ff969f);
- write_2338 (0xea0001a9, 0x80ff969f);
- write_2338 (0xeb0040b2, 0x0001c396);
- write_2338 (0xeb0040b3, 0x0001c396);
- write_2338 (0xec0040b2, 0x0001c396);
- write_2338 (0xea0001a9, 0x80ff94ff);
- write_2338 (0xea000151, 0x0088037f);
- write_2338 (0xea0000a9, 0x80ff94ff);
- write_2338 (0xea000051, 0x0088037f);
+ pch_iobp_update(0xea007f62, 0, 0x00590133);
+ pch_iobp_update(0xec007f62, 0, 0x00590133);
+ pch_iobp_update(0xec007f64, 0, 0x59555588);
+ pch_iobp_update(0xea0040b9, 0, 0x0001051c);
+ pch_iobp_update(0xeb0040a1, 0, 0x800084ff);
+ pch_iobp_update(0xec0040a1, 0, 0x800084ff);
+ pch_iobp_update(0xea004001, 0, 0x00008400);
+ pch_iobp_update(0xeb004002, 0, 0x40201758);
+ pch_iobp_update(0xec004002, 0, 0x40201758);
+ pch_iobp_update(0xea004002, 0, 0x00601758);
+ pch_iobp_update(0xea0040a1, 0, 0x810084ff);
+ pch_iobp_update(0xeb0040b1, 0, 0x0001c598);
+ pch_iobp_update(0xec0040b1, 0, 0x0001c598);
+ pch_iobp_update(0xeb0040b6, 0, 0x0001c598);
+ pch_iobp_update(0xea0000a9, 0, 0x80ff969f);
+ pch_iobp_update(0xea0001a9, 0, 0x80ff969f);
+ pch_iobp_update(0xeb0040b2, 0, 0x0001c396);
+ pch_iobp_update(0xeb0040b3, 0, 0x0001c396);
+ pch_iobp_update(0xec0040b2, 0, 0x0001c396);
+ pch_iobp_update(0xea0001a9, 0, 0x80ff94ff);
+ pch_iobp_update(0xea000151, 0, 0x0088037f);
+ pch_iobp_update(0xea0000a9, 0, 0x80ff94ff);
+ pch_iobp_update(0xea000051, 0, 0x0088037f);
- write_2338 (0xea007f05, 0x00010642);
- write_2338 (0xea0040b7, 0x0001c91c);
- write_2338 (0xea0040b8, 0x0001c91c);
- write_2338 (0xeb0040a1, 0x820084ff);
- write_2338 (0xec0040a1, 0x820084ff);
- write_2338 (0xea007f0a, 0xc2480000);
+ pch_iobp_update(0xea007f05, 0, 0x00010642);
+ pch_iobp_update(0xea0040b7, 0, 0x0001c91c);
+ pch_iobp_update(0xea0040b8, 0, 0x0001c91c);
+ pch_iobp_update(0xeb0040a1, 0, 0x820084ff);
+ pch_iobp_update(0xec0040a1, 0, 0x820084ff);
+ pch_iobp_update(0xea007f0a, 0, 0xc2480000);
- write_2338 (0xec00404d, 0x1ff177f);
- write_2338 (0xec000084, 0x5a600000);
- write_2338 (0xec000184, 0x5a600000);
- write_2338 (0xec000284, 0x5a600000);
- write_2338 (0xec000384, 0x5a600000);
- write_2338 (0xec000094, 0x000f0501);
- write_2338 (0xec000194, 0x000f0501);
- write_2338 (0xec000294, 0x000f0501);
- write_2338 (0xec000394, 0x000f0501);
- write_2338 (0xec000096, 0x00000001);
- write_2338 (0xec000196, 0x00000001);
- write_2338 (0xec000296, 0x00000001);
- write_2338 (0xec000396, 0x00000001);
- write_2338 (0xec000001, 0x00008c08);
- write_2338 (0xec000101, 0x00008c08);
- write_2338 (0xec000201, 0x00008c08);
- write_2338 (0xec000301, 0x00008c08);
- write_2338 (0xec0040b5, 0x0001c518);
- write_2338 (0xec000087, 0x06077597);
- write_2338 (0xec000187, 0x06077597);
- write_2338 (0xec000287, 0x06077597);
- write_2338 (0xec000387, 0x06077597);
- write_2338 (0xea000050, 0x00bb0157);
- write_2338 (0xea000150, 0x00bb0157);
- write_2338 (0xec007f60, 0x77777d77);
- write_2338 (0xea00008d, 0x01320000);
- write_2338 (0xea00018d, 0x01320000);
- write_2338 (0xec0007b2, 0x04514b5e);
- write_2338 (0xec00078c, 0x40000200);
- write_2338 (0xec000780, 0x02000020);
+ pch_iobp_update(0xec00404d, 0, 0x1ff177f);
+ pch_iobp_update(0xec000084, 0, 0x5a600000);
+ pch_iobp_update(0xec000184, 0, 0x5a600000);
+ pch_iobp_update(0xec000284, 0, 0x5a600000);
+ pch_iobp_update(0xec000384, 0, 0x5a600000);
+ pch_iobp_update(0xec000094, 0, 0x000f0501);
+ pch_iobp_update(0xec000194, 0, 0x000f0501);
+ pch_iobp_update(0xec000294, 0, 0x000f0501);
+ pch_iobp_update(0xec000394, 0, 0x000f0501);
+ pch_iobp_update(0xec000096, 0, 0x00000001);
+ pch_iobp_update(0xec000196, 0, 0x00000001);
+ pch_iobp_update(0xec000296, 0, 0x00000001);
+ pch_iobp_update(0xec000396, 0, 0x00000001);
+ pch_iobp_update(0xec000001, 0, 0x00008c08);
+ pch_iobp_update(0xec000101, 0, 0x00008c08);
+ pch_iobp_update(0xec000201, 0, 0x00008c08);
+ pch_iobp_update(0xec000301, 0, 0x00008c08);
+ pch_iobp_update(0xec0040b5, 0, 0x0001c518);
+ pch_iobp_update(0xec000087, 0, 0x06077597);
+ pch_iobp_update(0xec000187, 0, 0x06077597);
+ pch_iobp_update(0xec000287, 0, 0x06077597);
+ pch_iobp_update(0xec000387, 0, 0x06077597);
+ pch_iobp_update(0xea000050, 0, 0x00bb0157);
+ pch_iobp_update(0xea000150, 0, 0x00bb0157);
+ pch_iobp_update(0xec007f60, 0, 0x77777d77);
+ pch_iobp_update(0xea00008d, 0, 0x01320000);
+ pch_iobp_update(0xea00018d, 0, 0x01320000);
+ pch_iobp_update(0xec0007b2, 0, 0x04514b5e);
+ pch_iobp_update(0xec00078c, 0, 0x40000200);
+ pch_iobp_update(0xec000780, 0, 0x02000020);
init_dmi();
}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 28323ac..6848cda 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -59,6 +59,7 @@ void intel_pch_finalize_smm(void);
#endif
#if !defined(__ASSEMBLER__)
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
@@ -67,7 +68,6 @@ void pch_enable(device_t dev);
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if CONFIG_ELOG
void pch_log_state(void);
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